Verilog implementation of the SHA-1 cryptgraphic hash function

It contains a curated list of awesome RISC-V Resources.

Python interface for igraph

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

Multi-platform nightly builds of open source digital design and verification tools

SystemVerilog to Verilog conversion

Package manager and build abstraction tool for FPGA/ASIC development

Yosys Open SYnthesis Suite

Verilator open-source SystemVerilog simulator and lint system

Library of deep learning models and datasets designed to make deep learning more accessible and accelerate ML research.

Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

An open-source microcontroller system based on RISC-V

Python Backtesting library for trading strategies

從 RISC-V 處理器到 UNIX 作業系統

Python wrapper for TA-Lib (http://ta-lib.org/).

NOT MY CODE! Zeus trojan horse - leaked in 2011, I am not the author. This repository is for study purposes only, do not message me about your lame hacking attempts.

Open source code for AlphaFold.

Qiskit is an open-source SDK for working with quantum computers at the level of circuits, algorithms, and application modules.

Roadmap to becoming an Artificial Intelligence Expert in 2022

Super Resolution for images using deep learning.