forked from torvalds/linux
-
Notifications
You must be signed in to change notification settings - Fork 17
/
pinctrl-ocelot.c
1229 lines (1075 loc) · 30 KB
/
pinctrl-ocelot.c
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Microsemi SoCs pinctrl driver
*
* Author: <[email protected]>
* License: Dual MIT/GPL
* Copyright (c) 2017 Microsemi Corporation
*/
#include <linux/gpio/driver.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/of_device.h>
#include <linux/of_irq.h>
#include <linux/of_platform.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include "core.h"
#include "pinconf.h"
#include "pinmux.h"
#define ocelot_clrsetbits(addr, clear, set) \
writel((readl(addr) & ~(clear)) | (set), (addr))
/* PINCONFIG bits (sparx5 only) */
enum {
PINCONF_BIAS,
PINCONF_SCHMITT,
PINCONF_DRIVE_STRENGTH,
};
#define BIAS_PD_BIT BIT(4)
#define BIAS_PU_BIT BIT(3)
#define BIAS_BITS (BIAS_PD_BIT|BIAS_PU_BIT)
#define SCHMITT_BIT BIT(2)
#define DRIVE_BITS GENMASK(1, 0)
/* GPIO standard registers */
#define OCELOT_GPIO_OUT_SET 0x0
#define OCELOT_GPIO_OUT_CLR 0x4
#define OCELOT_GPIO_OUT 0x8
#define OCELOT_GPIO_IN 0xc
#define OCELOT_GPIO_OE 0x10
#define OCELOT_GPIO_INTR 0x14
#define OCELOT_GPIO_INTR_ENA 0x18
#define OCELOT_GPIO_INTR_IDENT 0x1c
#define OCELOT_GPIO_ALT0 0x20
#define OCELOT_GPIO_ALT1 0x24
#define OCELOT_GPIO_SD_MAP 0x28
#define OCELOT_FUNC_PER_PIN 4
enum {
FUNC_NONE,
FUNC_GPIO,
FUNC_IRQ0,
FUNC_IRQ0_IN,
FUNC_IRQ0_OUT,
FUNC_IRQ1,
FUNC_IRQ1_IN,
FUNC_IRQ1_OUT,
FUNC_EXT_IRQ,
FUNC_MIIM,
FUNC_PHY_LED,
FUNC_PCI_WAKE,
FUNC_MD,
FUNC_PTP0,
FUNC_PTP1,
FUNC_PTP2,
FUNC_PTP3,
FUNC_PWM,
FUNC_RECO_CLK,
FUNC_SFP,
FUNC_SG0,
FUNC_SG1,
FUNC_SG2,
FUNC_SI,
FUNC_SI2,
FUNC_TACHO,
FUNC_TWI,
FUNC_TWI2,
FUNC_TWI3,
FUNC_TWI_SCL_M,
FUNC_UART,
FUNC_UART2,
FUNC_UART3,
FUNC_PLL_STAT,
FUNC_EMMC,
FUNC_REF_CLK,
FUNC_RCVRD_CLK,
FUNC_MAX
};
static const char *const ocelot_function_names[] = {
[FUNC_NONE] = "none",
[FUNC_GPIO] = "gpio",
[FUNC_IRQ0] = "irq0",
[FUNC_IRQ0_IN] = "irq0_in",
[FUNC_IRQ0_OUT] = "irq0_out",
[FUNC_IRQ1] = "irq1",
[FUNC_IRQ1_IN] = "irq1_in",
[FUNC_IRQ1_OUT] = "irq1_out",
[FUNC_EXT_IRQ] = "ext_irq",
[FUNC_MIIM] = "miim",
[FUNC_PHY_LED] = "phy_led",
[FUNC_PCI_WAKE] = "pci_wake",
[FUNC_MD] = "md",
[FUNC_PTP0] = "ptp0",
[FUNC_PTP1] = "ptp1",
[FUNC_PTP2] = "ptp2",
[FUNC_PTP3] = "ptp3",
[FUNC_PWM] = "pwm",
[FUNC_RECO_CLK] = "reco_clk",
[FUNC_SFP] = "sfp",
[FUNC_SG0] = "sg0",
[FUNC_SG1] = "sg1",
[FUNC_SG2] = "sg2",
[FUNC_SI] = "si",
[FUNC_SI2] = "si2",
[FUNC_TACHO] = "tacho",
[FUNC_TWI] = "twi",
[FUNC_TWI2] = "twi2",
[FUNC_TWI3] = "twi3",
[FUNC_TWI_SCL_M] = "twi_scl_m",
[FUNC_UART] = "uart",
[FUNC_UART2] = "uart2",
[FUNC_UART3] = "uart3",
[FUNC_PLL_STAT] = "pll_stat",
[FUNC_EMMC] = "emmc",
[FUNC_REF_CLK] = "ref_clk",
[FUNC_RCVRD_CLK] = "rcvrd_clk",
};
struct ocelot_pmx_func {
const char **groups;
unsigned int ngroups;
};
struct ocelot_pin_caps {
unsigned int pin;
unsigned char functions[OCELOT_FUNC_PER_PIN];
};
struct ocelot_pinctrl {
struct device *dev;
struct pinctrl_dev *pctl;
struct gpio_chip gpio_chip;
struct regmap *map;
void __iomem *pincfg;
struct pinctrl_desc *desc;
struct ocelot_pmx_func func[FUNC_MAX];
u8 stride;
};
#define OCELOT_P(p, f0, f1, f2) \
static struct ocelot_pin_caps ocelot_pin_##p = { \
.pin = p, \
.functions = { \
FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_##f2, \
}, \
}
OCELOT_P(0, SG0, NONE, NONE);
OCELOT_P(1, SG0, NONE, NONE);
OCELOT_P(2, SG0, NONE, NONE);
OCELOT_P(3, SG0, NONE, NONE);
OCELOT_P(4, IRQ0_IN, IRQ0_OUT, TWI_SCL_M);
OCELOT_P(5, IRQ1_IN, IRQ1_OUT, PCI_WAKE);
OCELOT_P(6, UART, TWI_SCL_M, NONE);
OCELOT_P(7, UART, TWI_SCL_M, NONE);
OCELOT_P(8, SI, TWI_SCL_M, IRQ0_OUT);
OCELOT_P(9, SI, TWI_SCL_M, IRQ1_OUT);
OCELOT_P(10, PTP2, TWI_SCL_M, SFP);
OCELOT_P(11, PTP3, TWI_SCL_M, SFP);
OCELOT_P(12, UART2, TWI_SCL_M, SFP);
OCELOT_P(13, UART2, TWI_SCL_M, SFP);
OCELOT_P(14, MIIM, TWI_SCL_M, SFP);
OCELOT_P(15, MIIM, TWI_SCL_M, SFP);
OCELOT_P(16, TWI, NONE, SI);
OCELOT_P(17, TWI, TWI_SCL_M, SI);
OCELOT_P(18, PTP0, TWI_SCL_M, NONE);
OCELOT_P(19, PTP1, TWI_SCL_M, NONE);
OCELOT_P(20, RECO_CLK, TACHO, TWI_SCL_M);
OCELOT_P(21, RECO_CLK, PWM, TWI_SCL_M);
#define OCELOT_PIN(n) { \
.number = n, \
.name = "GPIO_"#n, \
.drv_data = &ocelot_pin_##n \
}
static const struct pinctrl_pin_desc ocelot_pins[] = {
OCELOT_PIN(0),
OCELOT_PIN(1),
OCELOT_PIN(2),
OCELOT_PIN(3),
OCELOT_PIN(4),
OCELOT_PIN(5),
OCELOT_PIN(6),
OCELOT_PIN(7),
OCELOT_PIN(8),
OCELOT_PIN(9),
OCELOT_PIN(10),
OCELOT_PIN(11),
OCELOT_PIN(12),
OCELOT_PIN(13),
OCELOT_PIN(14),
OCELOT_PIN(15),
OCELOT_PIN(16),
OCELOT_PIN(17),
OCELOT_PIN(18),
OCELOT_PIN(19),
OCELOT_PIN(20),
OCELOT_PIN(21),
};
#define JAGUAR2_P(p, f0, f1) \
static struct ocelot_pin_caps jaguar2_pin_##p = { \
.pin = p, \
.functions = { \
FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_NONE \
}, \
}
JAGUAR2_P(0, SG0, NONE);
JAGUAR2_P(1, SG0, NONE);
JAGUAR2_P(2, SG0, NONE);
JAGUAR2_P(3, SG0, NONE);
JAGUAR2_P(4, SG1, NONE);
JAGUAR2_P(5, SG1, NONE);
JAGUAR2_P(6, IRQ0_IN, IRQ0_OUT);
JAGUAR2_P(7, IRQ1_IN, IRQ1_OUT);
JAGUAR2_P(8, PTP0, NONE);
JAGUAR2_P(9, PTP1, NONE);
JAGUAR2_P(10, UART, NONE);
JAGUAR2_P(11, UART, NONE);
JAGUAR2_P(12, SG1, NONE);
JAGUAR2_P(13, SG1, NONE);
JAGUAR2_P(14, TWI, TWI_SCL_M);
JAGUAR2_P(15, TWI, NONE);
JAGUAR2_P(16, SI, TWI_SCL_M);
JAGUAR2_P(17, SI, TWI_SCL_M);
JAGUAR2_P(18, SI, TWI_SCL_M);
JAGUAR2_P(19, PCI_WAKE, NONE);
JAGUAR2_P(20, IRQ0_OUT, TWI_SCL_M);
JAGUAR2_P(21, IRQ1_OUT, TWI_SCL_M);
JAGUAR2_P(22, TACHO, NONE);
JAGUAR2_P(23, PWM, NONE);
JAGUAR2_P(24, UART2, NONE);
JAGUAR2_P(25, UART2, SI);
JAGUAR2_P(26, PTP2, SI);
JAGUAR2_P(27, PTP3, SI);
JAGUAR2_P(28, TWI2, SI);
JAGUAR2_P(29, TWI2, SI);
JAGUAR2_P(30, SG2, SI);
JAGUAR2_P(31, SG2, SI);
JAGUAR2_P(32, SG2, SI);
JAGUAR2_P(33, SG2, SI);
JAGUAR2_P(34, NONE, TWI_SCL_M);
JAGUAR2_P(35, NONE, TWI_SCL_M);
JAGUAR2_P(36, NONE, TWI_SCL_M);
JAGUAR2_P(37, NONE, TWI_SCL_M);
JAGUAR2_P(38, NONE, TWI_SCL_M);
JAGUAR2_P(39, NONE, TWI_SCL_M);
JAGUAR2_P(40, NONE, TWI_SCL_M);
JAGUAR2_P(41, NONE, TWI_SCL_M);
JAGUAR2_P(42, NONE, TWI_SCL_M);
JAGUAR2_P(43, NONE, TWI_SCL_M);
JAGUAR2_P(44, NONE, SFP);
JAGUAR2_P(45, NONE, SFP);
JAGUAR2_P(46, NONE, SFP);
JAGUAR2_P(47, NONE, SFP);
JAGUAR2_P(48, SFP, NONE);
JAGUAR2_P(49, SFP, SI);
JAGUAR2_P(50, SFP, SI);
JAGUAR2_P(51, SFP, SI);
JAGUAR2_P(52, SFP, NONE);
JAGUAR2_P(53, SFP, NONE);
JAGUAR2_P(54, SFP, NONE);
JAGUAR2_P(55, SFP, NONE);
JAGUAR2_P(56, MIIM, SFP);
JAGUAR2_P(57, MIIM, SFP);
JAGUAR2_P(58, MIIM, SFP);
JAGUAR2_P(59, MIIM, SFP);
JAGUAR2_P(60, NONE, NONE);
JAGUAR2_P(61, NONE, NONE);
JAGUAR2_P(62, NONE, NONE);
JAGUAR2_P(63, NONE, NONE);
#define JAGUAR2_PIN(n) { \
.number = n, \
.name = "GPIO_"#n, \
.drv_data = &jaguar2_pin_##n \
}
static const struct pinctrl_pin_desc jaguar2_pins[] = {
JAGUAR2_PIN(0),
JAGUAR2_PIN(1),
JAGUAR2_PIN(2),
JAGUAR2_PIN(3),
JAGUAR2_PIN(4),
JAGUAR2_PIN(5),
JAGUAR2_PIN(6),
JAGUAR2_PIN(7),
JAGUAR2_PIN(8),
JAGUAR2_PIN(9),
JAGUAR2_PIN(10),
JAGUAR2_PIN(11),
JAGUAR2_PIN(12),
JAGUAR2_PIN(13),
JAGUAR2_PIN(14),
JAGUAR2_PIN(15),
JAGUAR2_PIN(16),
JAGUAR2_PIN(17),
JAGUAR2_PIN(18),
JAGUAR2_PIN(19),
JAGUAR2_PIN(20),
JAGUAR2_PIN(21),
JAGUAR2_PIN(22),
JAGUAR2_PIN(23),
JAGUAR2_PIN(24),
JAGUAR2_PIN(25),
JAGUAR2_PIN(26),
JAGUAR2_PIN(27),
JAGUAR2_PIN(28),
JAGUAR2_PIN(29),
JAGUAR2_PIN(30),
JAGUAR2_PIN(31),
JAGUAR2_PIN(32),
JAGUAR2_PIN(33),
JAGUAR2_PIN(34),
JAGUAR2_PIN(35),
JAGUAR2_PIN(36),
JAGUAR2_PIN(37),
JAGUAR2_PIN(38),
JAGUAR2_PIN(39),
JAGUAR2_PIN(40),
JAGUAR2_PIN(41),
JAGUAR2_PIN(42),
JAGUAR2_PIN(43),
JAGUAR2_PIN(44),
JAGUAR2_PIN(45),
JAGUAR2_PIN(46),
JAGUAR2_PIN(47),
JAGUAR2_PIN(48),
JAGUAR2_PIN(49),
JAGUAR2_PIN(50),
JAGUAR2_PIN(51),
JAGUAR2_PIN(52),
JAGUAR2_PIN(53),
JAGUAR2_PIN(54),
JAGUAR2_PIN(55),
JAGUAR2_PIN(56),
JAGUAR2_PIN(57),
JAGUAR2_PIN(58),
JAGUAR2_PIN(59),
JAGUAR2_PIN(60),
JAGUAR2_PIN(61),
JAGUAR2_PIN(62),
JAGUAR2_PIN(63),
};
#define SPARX5_P(p, f0, f1, f2) \
static struct ocelot_pin_caps sparx5_pin_##p = { \
.pin = p, \
.functions = { \
FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_##f2 \
}, \
}
SPARX5_P(0, SG0, PLL_STAT, NONE);
SPARX5_P(1, SG0, NONE, NONE);
SPARX5_P(2, SG0, NONE, NONE);
SPARX5_P(3, SG0, NONE, NONE);
SPARX5_P(4, SG1, NONE, NONE);
SPARX5_P(5, SG1, NONE, NONE);
SPARX5_P(6, IRQ0_IN, IRQ0_OUT, SFP);
SPARX5_P(7, IRQ1_IN, IRQ1_OUT, SFP);
SPARX5_P(8, PTP0, NONE, SFP);
SPARX5_P(9, PTP1, SFP, TWI_SCL_M);
SPARX5_P(10, UART, NONE, NONE);
SPARX5_P(11, UART, NONE, NONE);
SPARX5_P(12, SG1, NONE, NONE);
SPARX5_P(13, SG1, NONE, NONE);
SPARX5_P(14, TWI, TWI_SCL_M, NONE);
SPARX5_P(15, TWI, NONE, NONE);
SPARX5_P(16, SI, TWI_SCL_M, SFP);
SPARX5_P(17, SI, TWI_SCL_M, SFP);
SPARX5_P(18, SI, TWI_SCL_M, SFP);
SPARX5_P(19, PCI_WAKE, TWI_SCL_M, SFP);
SPARX5_P(20, IRQ0_OUT, TWI_SCL_M, SFP);
SPARX5_P(21, IRQ1_OUT, TACHO, SFP);
SPARX5_P(22, TACHO, IRQ0_OUT, TWI_SCL_M);
SPARX5_P(23, PWM, UART3, TWI_SCL_M);
SPARX5_P(24, PTP2, UART3, TWI_SCL_M);
SPARX5_P(25, PTP3, SI, TWI_SCL_M);
SPARX5_P(26, UART2, SI, TWI_SCL_M);
SPARX5_P(27, UART2, SI, TWI_SCL_M);
SPARX5_P(28, TWI2, SI, SFP);
SPARX5_P(29, TWI2, SI, SFP);
SPARX5_P(30, SG2, SI, PWM);
SPARX5_P(31, SG2, SI, TWI_SCL_M);
SPARX5_P(32, SG2, SI, TWI_SCL_M);
SPARX5_P(33, SG2, SI, SFP);
SPARX5_P(34, NONE, TWI_SCL_M, EMMC);
SPARX5_P(35, SFP, TWI_SCL_M, EMMC);
SPARX5_P(36, SFP, TWI_SCL_M, EMMC);
SPARX5_P(37, SFP, NONE, EMMC);
SPARX5_P(38, NONE, TWI_SCL_M, EMMC);
SPARX5_P(39, SI2, TWI_SCL_M, EMMC);
SPARX5_P(40, SI2, TWI_SCL_M, EMMC);
SPARX5_P(41, SI2, TWI_SCL_M, EMMC);
SPARX5_P(42, SI2, TWI_SCL_M, EMMC);
SPARX5_P(43, SI2, TWI_SCL_M, EMMC);
SPARX5_P(44, SI, SFP, EMMC);
SPARX5_P(45, SI, SFP, EMMC);
SPARX5_P(46, NONE, SFP, EMMC);
SPARX5_P(47, NONE, SFP, EMMC);
SPARX5_P(48, TWI3, SI, SFP);
SPARX5_P(49, TWI3, NONE, SFP);
SPARX5_P(50, SFP, NONE, TWI_SCL_M);
SPARX5_P(51, SFP, SI, TWI_SCL_M);
SPARX5_P(52, SFP, MIIM, TWI_SCL_M);
SPARX5_P(53, SFP, MIIM, TWI_SCL_M);
SPARX5_P(54, SFP, PTP2, TWI_SCL_M);
SPARX5_P(55, SFP, PTP3, PCI_WAKE);
SPARX5_P(56, MIIM, SFP, TWI_SCL_M);
SPARX5_P(57, MIIM, SFP, TWI_SCL_M);
SPARX5_P(58, MIIM, SFP, TWI_SCL_M);
SPARX5_P(59, MIIM, SFP, NONE);
SPARX5_P(60, RECO_CLK, NONE, NONE);
SPARX5_P(61, RECO_CLK, NONE, NONE);
SPARX5_P(62, RECO_CLK, PLL_STAT, NONE);
SPARX5_P(63, RECO_CLK, NONE, NONE);
#define SPARX5_PIN(n) { \
.number = n, \
.name = "GPIO_"#n, \
.drv_data = &sparx5_pin_##n \
}
static const struct pinctrl_pin_desc sparx5_pins[] = {
SPARX5_PIN(0),
SPARX5_PIN(1),
SPARX5_PIN(2),
SPARX5_PIN(3),
SPARX5_PIN(4),
SPARX5_PIN(5),
SPARX5_PIN(6),
SPARX5_PIN(7),
SPARX5_PIN(8),
SPARX5_PIN(9),
SPARX5_PIN(10),
SPARX5_PIN(11),
SPARX5_PIN(12),
SPARX5_PIN(13),
SPARX5_PIN(14),
SPARX5_PIN(15),
SPARX5_PIN(16),
SPARX5_PIN(17),
SPARX5_PIN(18),
SPARX5_PIN(19),
SPARX5_PIN(20),
SPARX5_PIN(21),
SPARX5_PIN(22),
SPARX5_PIN(23),
SPARX5_PIN(24),
SPARX5_PIN(25),
SPARX5_PIN(26),
SPARX5_PIN(27),
SPARX5_PIN(28),
SPARX5_PIN(29),
SPARX5_PIN(30),
SPARX5_PIN(31),
SPARX5_PIN(32),
SPARX5_PIN(33),
SPARX5_PIN(34),
SPARX5_PIN(35),
SPARX5_PIN(36),
SPARX5_PIN(37),
SPARX5_PIN(38),
SPARX5_PIN(39),
SPARX5_PIN(40),
SPARX5_PIN(41),
SPARX5_PIN(42),
SPARX5_PIN(43),
SPARX5_PIN(44),
SPARX5_PIN(45),
SPARX5_PIN(46),
SPARX5_PIN(47),
SPARX5_PIN(48),
SPARX5_PIN(49),
SPARX5_PIN(50),
SPARX5_PIN(51),
SPARX5_PIN(52),
SPARX5_PIN(53),
SPARX5_PIN(54),
SPARX5_PIN(55),
SPARX5_PIN(56),
SPARX5_PIN(57),
SPARX5_PIN(58),
SPARX5_PIN(59),
SPARX5_PIN(60),
SPARX5_PIN(61),
SPARX5_PIN(62),
SPARX5_PIN(63),
};
static int ocelot_get_functions_count(struct pinctrl_dev *pctldev)
{
return ARRAY_SIZE(ocelot_function_names);
}
static const char *ocelot_get_function_name(struct pinctrl_dev *pctldev,
unsigned int function)
{
return ocelot_function_names[function];
}
static int ocelot_get_function_groups(struct pinctrl_dev *pctldev,
unsigned int function,
const char *const **groups,
unsigned *const num_groups)
{
struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
*groups = info->func[function].groups;
*num_groups = info->func[function].ngroups;
return 0;
}
static int ocelot_pin_function_idx(struct ocelot_pinctrl *info,
unsigned int pin, unsigned int function)
{
struct ocelot_pin_caps *p = info->desc->pins[pin].drv_data;
int i;
for (i = 0; i < OCELOT_FUNC_PER_PIN; i++) {
if (function == p->functions[i])
return i;
}
return -1;
}
#define REG_ALT(msb, info, p) (OCELOT_GPIO_ALT0 * (info)->stride + 4 * ((msb) + ((info)->stride * ((p) / 32))))
static int ocelot_pinmux_set_mux(struct pinctrl_dev *pctldev,
unsigned int selector, unsigned int group)
{
struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
struct ocelot_pin_caps *pin = info->desc->pins[group].drv_data;
unsigned int p = pin->pin % 32;
int f;
f = ocelot_pin_function_idx(info, group, selector);
if (f < 0)
return -EINVAL;
/*
* f is encoded on two bits.
* bit 0 of f goes in BIT(pin) of ALT[0], bit 1 of f goes in BIT(pin) of
* ALT[1]
* This is racy because both registers can't be updated at the same time
* but it doesn't matter much for now.
* Note: ALT0/ALT1 are organized specially for 64 gpio targets
*/
regmap_update_bits(info->map, REG_ALT(0, info, pin->pin),
BIT(p), f << p);
regmap_update_bits(info->map, REG_ALT(1, info, pin->pin),
BIT(p), f << (p - 1));
return 0;
}
#define REG(r, info, p) ((r) * (info)->stride + (4 * ((p) / 32)))
static int ocelot_gpio_set_direction(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range,
unsigned int pin, bool input)
{
struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
unsigned int p = pin % 32;
regmap_update_bits(info->map, REG(OCELOT_GPIO_OE, info, pin), BIT(p),
input ? 0 : BIT(p));
return 0;
}
static int ocelot_gpio_request_enable(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range,
unsigned int offset)
{
struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
unsigned int p = offset % 32;
regmap_update_bits(info->map, REG_ALT(0, info, offset),
BIT(p), 0);
regmap_update_bits(info->map, REG_ALT(1, info, offset),
BIT(p), 0);
return 0;
}
static const struct pinmux_ops ocelot_pmx_ops = {
.get_functions_count = ocelot_get_functions_count,
.get_function_name = ocelot_get_function_name,
.get_function_groups = ocelot_get_function_groups,
.set_mux = ocelot_pinmux_set_mux,
.gpio_set_direction = ocelot_gpio_set_direction,
.gpio_request_enable = ocelot_gpio_request_enable,
};
static int ocelot_pctl_get_groups_count(struct pinctrl_dev *pctldev)
{
struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
return info->desc->npins;
}
static const char *ocelot_pctl_get_group_name(struct pinctrl_dev *pctldev,
unsigned int group)
{
struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
return info->desc->pins[group].name;
}
static int ocelot_pctl_get_group_pins(struct pinctrl_dev *pctldev,
unsigned int group,
const unsigned int **pins,
unsigned int *num_pins)
{
struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
*pins = &info->desc->pins[group].number;
*num_pins = 1;
return 0;
}
static int ocelot_hw_get_value(struct ocelot_pinctrl *info,
unsigned int pin,
unsigned int reg,
int *val)
{
int ret = -EOPNOTSUPP;
if (info->pincfg) {
u32 regcfg = readl(info->pincfg + (pin * sizeof(u32)));
ret = 0;
switch (reg) {
case PINCONF_BIAS:
*val = regcfg & BIAS_BITS;
break;
case PINCONF_SCHMITT:
*val = regcfg & SCHMITT_BIT;
break;
case PINCONF_DRIVE_STRENGTH:
*val = regcfg & DRIVE_BITS;
break;
default:
ret = -EOPNOTSUPP;
break;
}
}
return ret;
}
static int ocelot_hw_set_value(struct ocelot_pinctrl *info,
unsigned int pin,
unsigned int reg,
int val)
{
int ret = -EOPNOTSUPP;
if (info->pincfg) {
void __iomem *regaddr = info->pincfg + (pin * sizeof(u32));
ret = 0;
switch (reg) {
case PINCONF_BIAS:
ocelot_clrsetbits(regaddr, BIAS_BITS, val);
break;
case PINCONF_SCHMITT:
ocelot_clrsetbits(regaddr, SCHMITT_BIT, val);
break;
case PINCONF_DRIVE_STRENGTH:
if (val <= 3)
ocelot_clrsetbits(regaddr, DRIVE_BITS, val);
else
ret = -EINVAL;
break;
default:
ret = -EOPNOTSUPP;
break;
}
}
return ret;
}
static int ocelot_pinconf_get(struct pinctrl_dev *pctldev,
unsigned int pin, unsigned long *config)
{
struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
u32 param = pinconf_to_config_param(*config);
int val, err;
switch (param) {
case PIN_CONFIG_BIAS_DISABLE:
case PIN_CONFIG_BIAS_PULL_UP:
case PIN_CONFIG_BIAS_PULL_DOWN:
err = ocelot_hw_get_value(info, pin, PINCONF_BIAS, &val);
if (err)
return err;
if (param == PIN_CONFIG_BIAS_DISABLE)
val = (val == 0 ? true : false);
else if (param == PIN_CONFIG_BIAS_PULL_DOWN)
val = (val & BIAS_PD_BIT ? true : false);
else /* PIN_CONFIG_BIAS_PULL_UP */
val = (val & BIAS_PU_BIT ? true : false);
break;
case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
err = ocelot_hw_get_value(info, pin, PINCONF_SCHMITT, &val);
if (err)
return err;
val = (val & SCHMITT_BIT ? true : false);
break;
case PIN_CONFIG_DRIVE_STRENGTH:
err = ocelot_hw_get_value(info, pin, PINCONF_DRIVE_STRENGTH,
&val);
if (err)
return err;
break;
case PIN_CONFIG_OUTPUT:
err = regmap_read(info->map, REG(OCELOT_GPIO_OUT, info, pin),
&val);
if (err)
return err;
val = !!(val & BIT(pin % 32));
break;
case PIN_CONFIG_INPUT_ENABLE:
case PIN_CONFIG_OUTPUT_ENABLE:
err = regmap_read(info->map, REG(OCELOT_GPIO_OE, info, pin),
&val);
if (err)
return err;
val = val & BIT(pin % 32);
if (param == PIN_CONFIG_OUTPUT_ENABLE)
val = !!val;
else
val = !val;
break;
default:
return -EOPNOTSUPP;
}
*config = pinconf_to_config_packed(param, val);
return 0;
}
static int ocelot_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
unsigned long *configs, unsigned int num_configs)
{
struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
u32 param, arg, p;
int cfg, err = 0;
for (cfg = 0; cfg < num_configs; cfg++) {
param = pinconf_to_config_param(configs[cfg]);
arg = pinconf_to_config_argument(configs[cfg]);
switch (param) {
case PIN_CONFIG_BIAS_DISABLE:
case PIN_CONFIG_BIAS_PULL_UP:
case PIN_CONFIG_BIAS_PULL_DOWN:
arg = (param == PIN_CONFIG_BIAS_DISABLE) ? 0 :
(param == PIN_CONFIG_BIAS_PULL_UP) ? BIAS_PU_BIT :
BIAS_PD_BIT;
err = ocelot_hw_set_value(info, pin, PINCONF_BIAS, arg);
if (err)
goto err;
break;
case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
arg = arg ? SCHMITT_BIT : 0;
err = ocelot_hw_set_value(info, pin, PINCONF_SCHMITT,
arg);
if (err)
goto err;
break;
case PIN_CONFIG_DRIVE_STRENGTH:
err = ocelot_hw_set_value(info, pin,
PINCONF_DRIVE_STRENGTH,
arg);
if (err)
goto err;
break;
case PIN_CONFIG_OUTPUT_ENABLE:
case PIN_CONFIG_INPUT_ENABLE:
case PIN_CONFIG_OUTPUT:
p = pin % 32;
if (arg)
regmap_write(info->map,
REG(OCELOT_GPIO_OUT_SET, info,
pin),
BIT(p));
else
regmap_write(info->map,
REG(OCELOT_GPIO_OUT_CLR, info,
pin),
BIT(p));
regmap_update_bits(info->map,
REG(OCELOT_GPIO_OE, info, pin),
BIT(p),
param == PIN_CONFIG_INPUT_ENABLE ?
0 : BIT(p));
break;
default:
err = -EOPNOTSUPP;
}
}
err:
return err;
}
static const struct pinconf_ops ocelot_confops = {
.is_generic = true,
.pin_config_get = ocelot_pinconf_get,
.pin_config_set = ocelot_pinconf_set,
.pin_config_config_dbg_show = pinconf_generic_dump_config,
};
static const struct pinctrl_ops ocelot_pctl_ops = {
.get_groups_count = ocelot_pctl_get_groups_count,
.get_group_name = ocelot_pctl_get_group_name,
.get_group_pins = ocelot_pctl_get_group_pins,
.dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
.dt_free_map = pinconf_generic_dt_free_map,
};
static struct pinctrl_desc ocelot_desc = {
.name = "ocelot-pinctrl",
.pins = ocelot_pins,
.npins = ARRAY_SIZE(ocelot_pins),
.pctlops = &ocelot_pctl_ops,
.pmxops = &ocelot_pmx_ops,
.owner = THIS_MODULE,
};
static struct pinctrl_desc jaguar2_desc = {
.name = "jaguar2-pinctrl",
.pins = jaguar2_pins,
.npins = ARRAY_SIZE(jaguar2_pins),
.pctlops = &ocelot_pctl_ops,
.pmxops = &ocelot_pmx_ops,
.owner = THIS_MODULE,
};
static struct pinctrl_desc sparx5_desc = {
.name = "sparx5-pinctrl",
.pins = sparx5_pins,
.npins = ARRAY_SIZE(sparx5_pins),
.pctlops = &ocelot_pctl_ops,
.pmxops = &ocelot_pmx_ops,
.confops = &ocelot_confops,
.owner = THIS_MODULE,
};
static int ocelot_create_group_func_map(struct device *dev,
struct ocelot_pinctrl *info)
{
int f, npins, i;
u8 *pins = kcalloc(info->desc->npins, sizeof(u8), GFP_KERNEL);
if (!pins)
return -ENOMEM;
for (f = 0; f < FUNC_MAX; f++) {
for (npins = 0, i = 0; i < info->desc->npins; i++) {
if (ocelot_pin_function_idx(info, i, f) >= 0)
pins[npins++] = i;
}
if (!npins)
continue;
info->func[f].ngroups = npins;
info->func[f].groups = devm_kcalloc(dev, npins, sizeof(char *),
GFP_KERNEL);
if (!info->func[f].groups) {
kfree(pins);
return -ENOMEM;
}
for (i = 0; i < npins; i++)
info->func[f].groups[i] =
info->desc->pins[pins[i]].name;
}
kfree(pins);
return 0;
}
static int ocelot_pinctrl_register(struct platform_device *pdev,
struct ocelot_pinctrl *info)
{
int ret;
ret = ocelot_create_group_func_map(&pdev->dev, info);
if (ret) {
dev_err(&pdev->dev, "Unable to create group func map.\n");
return ret;
}
info->pctl = devm_pinctrl_register(&pdev->dev, info->desc, info);
if (IS_ERR(info->pctl)) {
dev_err(&pdev->dev, "Failed to register pinctrl\n");
return PTR_ERR(info->pctl);
}
return 0;
}
static int ocelot_gpio_get(struct gpio_chip *chip, unsigned int offset)
{
struct ocelot_pinctrl *info = gpiochip_get_data(chip);
unsigned int val;
regmap_read(info->map, REG(OCELOT_GPIO_IN, info, offset), &val);
return !!(val & BIT(offset % 32));
}
static void ocelot_gpio_set(struct gpio_chip *chip, unsigned int offset,
int value)
{
struct ocelot_pinctrl *info = gpiochip_get_data(chip);
if (value)
regmap_write(info->map, REG(OCELOT_GPIO_OUT_SET, info, offset),
BIT(offset % 32));
else
regmap_write(info->map, REG(OCELOT_GPIO_OUT_CLR, info, offset),
BIT(offset % 32));
}
static int ocelot_gpio_get_direction(struct gpio_chip *chip,
unsigned int offset)
{
struct ocelot_pinctrl *info = gpiochip_get_data(chip);
unsigned int val;
regmap_read(info->map, REG(OCELOT_GPIO_OE, info, offset), &val);
if (val & BIT(offset % 32))
return GPIO_LINE_DIRECTION_OUT;
return GPIO_LINE_DIRECTION_IN;
}
static int ocelot_gpio_direction_input(struct gpio_chip *chip,
unsigned int offset)
{
return pinctrl_gpio_direction_input(chip->base + offset);
}
static int ocelot_gpio_direction_output(struct gpio_chip *chip,
unsigned int offset, int value)
{