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sparx5_serdes_regs.h
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sparx5_serdes_regs.h
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/* SPDX-License-Identifier: GPL-2.0+
* Microchip Sparx5 SerDes driver
*
* Copyright (c) 2020 Microchip Technology Inc.
*/
/* This file is autogenerated by cml-utils 2020-11-16 13:11:27 +0100.
* Commit ID: 13bdf073131d8bf40c54901df6988ae4e9c8f29f
*/
#ifndef _SPARX5_SERDES_REGS_H_
#define _SPARX5_SERDES_REGS_H_
#include <linux/bitfield.h>
#include <linux/types.h>
#include <linux/bug.h>
enum sparx5_serdes_target {
TARGET_SD10G_LANE = 200,
TARGET_SD25G_LANE = 212,
TARGET_SD6G_LANE = 233,
TARGET_SD_CMU = 248,
TARGET_SD_CMU_CFG = 262,
TARGET_SD_LANE = 276,
TARGET_SD_LANE_25G = 301,
NUM_TARGETS = 332
};
#define __REG(...) __VA_ARGS__
/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_01 */
#define SD10G_LANE_LANE_01(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 4, 0, 1, 4)
#define SD10G_LANE_LANE_01_CFG_PMA_TX_CK_BITWIDTH_2_0 GENMASK(2, 0)
#define SD10G_LANE_LANE_01_CFG_PMA_TX_CK_BITWIDTH_2_0_SET(x)\
FIELD_PREP(SD10G_LANE_LANE_01_CFG_PMA_TX_CK_BITWIDTH_2_0, x)
#define SD10G_LANE_LANE_01_CFG_PMA_TX_CK_BITWIDTH_2_0_GET(x)\
FIELD_GET(SD10G_LANE_LANE_01_CFG_PMA_TX_CK_BITWIDTH_2_0, x)
#define SD10G_LANE_LANE_01_CFG_RXDET_EN BIT(4)
#define SD10G_LANE_LANE_01_CFG_RXDET_EN_SET(x)\
FIELD_PREP(SD10G_LANE_LANE_01_CFG_RXDET_EN, x)
#define SD10G_LANE_LANE_01_CFG_RXDET_EN_GET(x)\
FIELD_GET(SD10G_LANE_LANE_01_CFG_RXDET_EN, x)
#define SD10G_LANE_LANE_01_CFG_RXDET_STR BIT(5)
#define SD10G_LANE_LANE_01_CFG_RXDET_STR_SET(x)\
FIELD_PREP(SD10G_LANE_LANE_01_CFG_RXDET_STR, x)
#define SD10G_LANE_LANE_01_CFG_RXDET_STR_GET(x)\
FIELD_GET(SD10G_LANE_LANE_01_CFG_RXDET_STR, x)
/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_02 */
#define SD10G_LANE_LANE_02(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 8, 0, 1, 4)
#define SD10G_LANE_LANE_02_CFG_EN_ADV BIT(0)
#define SD10G_LANE_LANE_02_CFG_EN_ADV_SET(x)\
FIELD_PREP(SD10G_LANE_LANE_02_CFG_EN_ADV, x)
#define SD10G_LANE_LANE_02_CFG_EN_ADV_GET(x)\
FIELD_GET(SD10G_LANE_LANE_02_CFG_EN_ADV, x)
#define SD10G_LANE_LANE_02_CFG_EN_MAIN BIT(1)
#define SD10G_LANE_LANE_02_CFG_EN_MAIN_SET(x)\
FIELD_PREP(SD10G_LANE_LANE_02_CFG_EN_MAIN, x)
#define SD10G_LANE_LANE_02_CFG_EN_MAIN_GET(x)\
FIELD_GET(SD10G_LANE_LANE_02_CFG_EN_MAIN, x)
#define SD10G_LANE_LANE_02_CFG_EN_DLY BIT(2)
#define SD10G_LANE_LANE_02_CFG_EN_DLY_SET(x)\
FIELD_PREP(SD10G_LANE_LANE_02_CFG_EN_DLY, x)
#define SD10G_LANE_LANE_02_CFG_EN_DLY_GET(x)\
FIELD_GET(SD10G_LANE_LANE_02_CFG_EN_DLY, x)
#define SD10G_LANE_LANE_02_CFG_EN_DLY2 BIT(3)
#define SD10G_LANE_LANE_02_CFG_EN_DLY2_SET(x)\
FIELD_PREP(SD10G_LANE_LANE_02_CFG_EN_DLY2, x)
#define SD10G_LANE_LANE_02_CFG_EN_DLY2_GET(x)\
FIELD_GET(SD10G_LANE_LANE_02_CFG_EN_DLY2, x)
#define SD10G_LANE_LANE_02_CFG_TAP_ADV_3_0 GENMASK(7, 4)
#define SD10G_LANE_LANE_02_CFG_TAP_ADV_3_0_SET(x)\
FIELD_PREP(SD10G_LANE_LANE_02_CFG_TAP_ADV_3_0, x)
#define SD10G_LANE_LANE_02_CFG_TAP_ADV_3_0_GET(x)\
FIELD_GET(SD10G_LANE_LANE_02_CFG_TAP_ADV_3_0, x)
/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_03 */
#define SD10G_LANE_LANE_03(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 12, 0, 1, 4)
#define SD10G_LANE_LANE_03_CFG_TAP_MAIN BIT(0)
#define SD10G_LANE_LANE_03_CFG_TAP_MAIN_SET(x)\
FIELD_PREP(SD10G_LANE_LANE_03_CFG_TAP_MAIN, x)
#define SD10G_LANE_LANE_03_CFG_TAP_MAIN_GET(x)\
FIELD_GET(SD10G_LANE_LANE_03_CFG_TAP_MAIN, x)
/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_04 */
#define SD10G_LANE_LANE_04(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 16, 0, 1, 4)
#define SD10G_LANE_LANE_04_CFG_TAP_DLY_4_0 GENMASK(4, 0)
#define SD10G_LANE_LANE_04_CFG_TAP_DLY_4_0_SET(x)\
FIELD_PREP(SD10G_LANE_LANE_04_CFG_TAP_DLY_4_0, x)
#define SD10G_LANE_LANE_04_CFG_TAP_DLY_4_0_GET(x)\
FIELD_GET(SD10G_LANE_LANE_04_CFG_TAP_DLY_4_0, x)
/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_06 */
#define SD10G_LANE_LANE_06(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 24, 0, 1, 4)
#define SD10G_LANE_LANE_06_CFG_PD_DRIVER BIT(0)
#define SD10G_LANE_LANE_06_CFG_PD_DRIVER_SET(x)\
FIELD_PREP(SD10G_LANE_LANE_06_CFG_PD_DRIVER, x)
#define SD10G_LANE_LANE_06_CFG_PD_DRIVER_GET(x)\
FIELD_GET(SD10G_LANE_LANE_06_CFG_PD_DRIVER, x)
#define SD10G_LANE_LANE_06_CFG_PD_CLK BIT(1)
#define SD10G_LANE_LANE_06_CFG_PD_CLK_SET(x)\
FIELD_PREP(SD10G_LANE_LANE_06_CFG_PD_CLK, x)
#define SD10G_LANE_LANE_06_CFG_PD_CLK_GET(x)\
FIELD_GET(SD10G_LANE_LANE_06_CFG_PD_CLK, x)
#define SD10G_LANE_LANE_06_CFG_PD_CML BIT(2)
#define SD10G_LANE_LANE_06_CFG_PD_CML_SET(x)\
FIELD_PREP(SD10G_LANE_LANE_06_CFG_PD_CML, x)
#define SD10G_LANE_LANE_06_CFG_PD_CML_GET(x)\
FIELD_GET(SD10G_LANE_LANE_06_CFG_PD_CML, x)
#define SD10G_LANE_LANE_06_CFG_TX2RX_LP_EN BIT(3)
#define SD10G_LANE_LANE_06_CFG_TX2RX_LP_EN_SET(x)\
FIELD_PREP(SD10G_LANE_LANE_06_CFG_TX2RX_LP_EN, x)
#define SD10G_LANE_LANE_06_CFG_TX2RX_LP_EN_GET(x)\
FIELD_GET(SD10G_LANE_LANE_06_CFG_TX2RX_LP_EN, x)
#define SD10G_LANE_LANE_06_CFG_RX2TX_LP_EN BIT(4)
#define SD10G_LANE_LANE_06_CFG_RX2TX_LP_EN_SET(x)\
FIELD_PREP(SD10G_LANE_LANE_06_CFG_RX2TX_LP_EN, x)
#define SD10G_LANE_LANE_06_CFG_RX2TX_LP_EN_GET(x)\
FIELD_GET(SD10G_LANE_LANE_06_CFG_RX2TX_LP_EN, x)
#define SD10G_LANE_LANE_06_CFG_EN_PREEMPH BIT(5)
#define SD10G_LANE_LANE_06_CFG_EN_PREEMPH_SET(x)\
FIELD_PREP(SD10G_LANE_LANE_06_CFG_EN_PREEMPH, x)
#define SD10G_LANE_LANE_06_CFG_EN_PREEMPH_GET(x)\
FIELD_GET(SD10G_LANE_LANE_06_CFG_EN_PREEMPH, x)
/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_0B */
#define SD10G_LANE_LANE_0B(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 44, 0, 1, 4)
#define SD10G_LANE_LANE_0B_CFG_EQ_RES_3_0 GENMASK(3, 0)
#define SD10G_LANE_LANE_0B_CFG_EQ_RES_3_0_SET(x)\
FIELD_PREP(SD10G_LANE_LANE_0B_CFG_EQ_RES_3_0, x)
#define SD10G_LANE_LANE_0B_CFG_EQ_RES_3_0_GET(x)\
FIELD_GET(SD10G_LANE_LANE_0B_CFG_EQ_RES_3_0, x)
#define SD10G_LANE_LANE_0B_CFG_PD_CTLE BIT(4)
#define SD10G_LANE_LANE_0B_CFG_PD_CTLE_SET(x)\
FIELD_PREP(SD10G_LANE_LANE_0B_CFG_PD_CTLE, x)
#define SD10G_LANE_LANE_0B_CFG_PD_CTLE_GET(x)\
FIELD_GET(SD10G_LANE_LANE_0B_CFG_PD_CTLE, x)
#define SD10G_LANE_LANE_0B_CFG_CTLE_TP_EN BIT(5)
#define SD10G_LANE_LANE_0B_CFG_CTLE_TP_EN_SET(x)\
FIELD_PREP(SD10G_LANE_LANE_0B_CFG_CTLE_TP_EN, x)
#define SD10G_LANE_LANE_0B_CFG_CTLE_TP_EN_GET(x)\
FIELD_GET(SD10G_LANE_LANE_0B_CFG_CTLE_TP_EN, x)
#define SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_AFE BIT(6)
#define SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_AFE_SET(x)\
FIELD_PREP(SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_AFE, x)
#define SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_AFE_GET(x)\
FIELD_GET(SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_AFE, x)
#define SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_SQ BIT(7)
#define SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_SQ_SET(x)\
FIELD_PREP(SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_SQ, x)
#define SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_SQ_GET(x)\
FIELD_GET(SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_SQ, x)
/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_0C */
#define SD10G_LANE_LANE_0C(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 48, 0, 1, 4)
#define SD10G_LANE_LANE_0C_CFG_OSCAL_AFE BIT(0)
#define SD10G_LANE_LANE_0C_CFG_OSCAL_AFE_SET(x)\
FIELD_PREP(SD10G_LANE_LANE_0C_CFG_OSCAL_AFE, x)
#define SD10G_LANE_LANE_0C_CFG_OSCAL_AFE_GET(x)\
FIELD_GET(SD10G_LANE_LANE_0C_CFG_OSCAL_AFE, x)
#define SD10G_LANE_LANE_0C_CFG_OSCAL_SQ BIT(1)
#define SD10G_LANE_LANE_0C_CFG_OSCAL_SQ_SET(x)\
FIELD_PREP(SD10G_LANE_LANE_0C_CFG_OSCAL_SQ, x)
#define SD10G_LANE_LANE_0C_CFG_OSCAL_SQ_GET(x)\
FIELD_GET(SD10G_LANE_LANE_0C_CFG_OSCAL_SQ, x)
#define SD10G_LANE_LANE_0C_CFG_OSDAC_2X_AFE BIT(2)
#define SD10G_LANE_LANE_0C_CFG_OSDAC_2X_AFE_SET(x)\
FIELD_PREP(SD10G_LANE_LANE_0C_CFG_OSDAC_2X_AFE, x)
#define SD10G_LANE_LANE_0C_CFG_OSDAC_2X_AFE_GET(x)\
FIELD_GET(SD10G_LANE_LANE_0C_CFG_OSDAC_2X_AFE, x)
#define SD10G_LANE_LANE_0C_CFG_OSDAC_2X_SQ BIT(3)
#define SD10G_LANE_LANE_0C_CFG_OSDAC_2X_SQ_SET(x)\
FIELD_PREP(SD10G_LANE_LANE_0C_CFG_OSDAC_2X_SQ, x)
#define SD10G_LANE_LANE_0C_CFG_OSDAC_2X_SQ_GET(x)\
FIELD_GET(SD10G_LANE_LANE_0C_CFG_OSDAC_2X_SQ, x)
#define SD10G_LANE_LANE_0C_CFG_PD_OSDAC_AFE BIT(4)
#define SD10G_LANE_LANE_0C_CFG_PD_OSDAC_AFE_SET(x)\
FIELD_PREP(SD10G_LANE_LANE_0C_CFG_PD_OSDAC_AFE, x)
#define SD10G_LANE_LANE_0C_CFG_PD_OSDAC_AFE_GET(x)\
FIELD_GET(SD10G_LANE_LANE_0C_CFG_PD_OSDAC_AFE, x)
#define SD10G_LANE_LANE_0C_CFG_PD_OSDAC_SQ BIT(5)
#define SD10G_LANE_LANE_0C_CFG_PD_OSDAC_SQ_SET(x)\
FIELD_PREP(SD10G_LANE_LANE_0C_CFG_PD_OSDAC_SQ, x)
#define SD10G_LANE_LANE_0C_CFG_PD_OSDAC_SQ_GET(x)\
FIELD_GET(SD10G_LANE_LANE_0C_CFG_PD_OSDAC_SQ, x)
#define SD10G_LANE_LANE_0C_CFG_PD_RX_LS BIT(6)
#define SD10G_LANE_LANE_0C_CFG_PD_RX_LS_SET(x)\
FIELD_PREP(SD10G_LANE_LANE_0C_CFG_PD_RX_LS, x)
#define SD10G_LANE_LANE_0C_CFG_PD_RX_LS_GET(x)\
FIELD_GET(SD10G_LANE_LANE_0C_CFG_PD_RX_LS, x)
#define SD10G_LANE_LANE_0C_CFG_RX_PCIE_GEN12 BIT(7)
#define SD10G_LANE_LANE_0C_CFG_RX_PCIE_GEN12_SET(x)\
FIELD_PREP(SD10G_LANE_LANE_0C_CFG_RX_PCIE_GEN12, x)
#define SD10G_LANE_LANE_0C_CFG_RX_PCIE_GEN12_GET(x)\
FIELD_GET(SD10G_LANE_LANE_0C_CFG_RX_PCIE_GEN12, x)
/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_0D */
#define SD10G_LANE_LANE_0D(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 52, 0, 1, 4)
#define SD10G_LANE_LANE_0D_CFG_CTLE_M_THR_1_0 GENMASK(1, 0)
#define SD10G_LANE_LANE_0D_CFG_CTLE_M_THR_1_0_SET(x)\
FIELD_PREP(SD10G_LANE_LANE_0D_CFG_CTLE_M_THR_1_0, x)
#define SD10G_LANE_LANE_0D_CFG_CTLE_M_THR_1_0_GET(x)\
FIELD_GET(SD10G_LANE_LANE_0D_CFG_CTLE_M_THR_1_0, x)
#define SD10G_LANE_LANE_0D_CFG_EQR_BYP BIT(4)
#define SD10G_LANE_LANE_0D_CFG_EQR_BYP_SET(x)\
FIELD_PREP(SD10G_LANE_LANE_0D_CFG_EQR_BYP, x)
#define SD10G_LANE_LANE_0D_CFG_EQR_BYP_GET(x)\
FIELD_GET(SD10G_LANE_LANE_0D_CFG_EQR_BYP, x)
/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_0E */
#define SD10G_LANE_LANE_0E(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 56, 0, 1, 4)
#define SD10G_LANE_LANE_0E_CFG_EQC_FORCE_3_0 GENMASK(3, 0)
#define SD10G_LANE_LANE_0E_CFG_EQC_FORCE_3_0_SET(x)\
FIELD_PREP(SD10G_LANE_LANE_0E_CFG_EQC_FORCE_3_0, x)
#define SD10G_LANE_LANE_0E_CFG_EQC_FORCE_3_0_GET(x)\
FIELD_GET(SD10G_LANE_LANE_0E_CFG_EQC_FORCE_3_0, x)
#define SD10G_LANE_LANE_0E_CFG_RXLB_EN BIT(4)
#define SD10G_LANE_LANE_0E_CFG_RXLB_EN_SET(x)\
FIELD_PREP(SD10G_LANE_LANE_0E_CFG_RXLB_EN, x)
#define SD10G_LANE_LANE_0E_CFG_RXLB_EN_GET(x)\
FIELD_GET(SD10G_LANE_LANE_0E_CFG_RXLB_EN, x)
#define SD10G_LANE_LANE_0E_CFG_TXLB_EN BIT(5)
#define SD10G_LANE_LANE_0E_CFG_TXLB_EN_SET(x)\
FIELD_PREP(SD10G_LANE_LANE_0E_CFG_TXLB_EN, x)
#define SD10G_LANE_LANE_0E_CFG_TXLB_EN_GET(x)\
FIELD_GET(SD10G_LANE_LANE_0E_CFG_TXLB_EN, x)
#define SD10G_LANE_LANE_0E_CFG_SUM_SETCM_EN BIT(6)
#define SD10G_LANE_LANE_0E_CFG_SUM_SETCM_EN_SET(x)\
FIELD_PREP(SD10G_LANE_LANE_0E_CFG_SUM_SETCM_EN, x)
#define SD10G_LANE_LANE_0E_CFG_SUM_SETCM_EN_GET(x)\
FIELD_GET(SD10G_LANE_LANE_0E_CFG_SUM_SETCM_EN, x)
/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_0F */
#define SD10G_LANE_LANE_0F(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 60, 0, 1, 4)
#define SD10G_LANE_LANE_0F_R_CDR_M_GEN1_7_0 GENMASK(7, 0)
#define SD10G_LANE_LANE_0F_R_CDR_M_GEN1_7_0_SET(x)\
FIELD_PREP(SD10G_LANE_LANE_0F_R_CDR_M_GEN1_7_0, x)
#define SD10G_LANE_LANE_0F_R_CDR_M_GEN1_7_0_GET(x)\
FIELD_GET(SD10G_LANE_LANE_0F_R_CDR_M_GEN1_7_0, x)
/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_13 */
#define SD10G_LANE_LANE_13(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 76, 0, 1, 4)
#define SD10G_LANE_LANE_13_CFG_DCDR_PD BIT(0)
#define SD10G_LANE_LANE_13_CFG_DCDR_PD_SET(x)\
FIELD_PREP(SD10G_LANE_LANE_13_CFG_DCDR_PD, x)
#define SD10G_LANE_LANE_13_CFG_DCDR_PD_GET(x)\
FIELD_GET(SD10G_LANE_LANE_13_CFG_DCDR_PD, x)
#define SD10G_LANE_LANE_13_CFG_PHID_1T BIT(1)
#define SD10G_LANE_LANE_13_CFG_PHID_1T_SET(x)\
FIELD_PREP(SD10G_LANE_LANE_13_CFG_PHID_1T, x)
#define SD10G_LANE_LANE_13_CFG_PHID_1T_GET(x)\
FIELD_GET(SD10G_LANE_LANE_13_CFG_PHID_1T, x)
#define SD10G_LANE_LANE_13_CFG_CDRCK_EN BIT(2)
#define SD10G_LANE_LANE_13_CFG_CDRCK_EN_SET(x)\
FIELD_PREP(SD10G_LANE_LANE_13_CFG_CDRCK_EN, x)
#define SD10G_LANE_LANE_13_CFG_CDRCK_EN_GET(x)\
FIELD_GET(SD10G_LANE_LANE_13_CFG_CDRCK_EN, x)
/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_14 */
#define SD10G_LANE_LANE_14(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 80, 0, 1, 4)
#define SD10G_LANE_LANE_14_CFG_PI_EXT_DAC_7_0 GENMASK(7, 0)
#define SD10G_LANE_LANE_14_CFG_PI_EXT_DAC_7_0_SET(x)\
FIELD_PREP(SD10G_LANE_LANE_14_CFG_PI_EXT_DAC_7_0, x)
#define SD10G_LANE_LANE_14_CFG_PI_EXT_DAC_7_0_GET(x)\
FIELD_GET(SD10G_LANE_LANE_14_CFG_PI_EXT_DAC_7_0, x)
/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_15 */
#define SD10G_LANE_LANE_15(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 84, 0, 1, 4)
#define SD10G_LANE_LANE_15_CFG_PI_EXT_DAC_15_8 GENMASK(7, 0)
#define SD10G_LANE_LANE_15_CFG_PI_EXT_DAC_15_8_SET(x)\
FIELD_PREP(SD10G_LANE_LANE_15_CFG_PI_EXT_DAC_15_8, x)
#define SD10G_LANE_LANE_15_CFG_PI_EXT_DAC_15_8_GET(x)\
FIELD_GET(SD10G_LANE_LANE_15_CFG_PI_EXT_DAC_15_8, x)
/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_16 */
#define SD10G_LANE_LANE_16(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 88, 0, 1, 4)
#define SD10G_LANE_LANE_16_CFG_PI_EXT_DAC_23_16 GENMASK(7, 0)
#define SD10G_LANE_LANE_16_CFG_PI_EXT_DAC_23_16_SET(x)\
FIELD_PREP(SD10G_LANE_LANE_16_CFG_PI_EXT_DAC_23_16, x)
#define SD10G_LANE_LANE_16_CFG_PI_EXT_DAC_23_16_GET(x)\
FIELD_GET(SD10G_LANE_LANE_16_CFG_PI_EXT_DAC_23_16, x)
/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_1A */
#define SD10G_LANE_LANE_1A(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 104, 0, 1, 4)
#define SD10G_LANE_LANE_1A_CFG_PI_R_SCAN_EN BIT(0)
#define SD10G_LANE_LANE_1A_CFG_PI_R_SCAN_EN_SET(x)\
FIELD_PREP(SD10G_LANE_LANE_1A_CFG_PI_R_SCAN_EN, x)
#define SD10G_LANE_LANE_1A_CFG_PI_R_SCAN_EN_GET(x)\
FIELD_GET(SD10G_LANE_LANE_1A_CFG_PI_R_SCAN_EN, x)
#define SD10G_LANE_LANE_1A_CFG_PI_EN BIT(1)
#define SD10G_LANE_LANE_1A_CFG_PI_EN_SET(x)\
FIELD_PREP(SD10G_LANE_LANE_1A_CFG_PI_EN, x)
#define SD10G_LANE_LANE_1A_CFG_PI_EN_GET(x)\
FIELD_GET(SD10G_LANE_LANE_1A_CFG_PI_EN, x)
#define SD10G_LANE_LANE_1A_CFG_PI_DFE_EN BIT(2)
#define SD10G_LANE_LANE_1A_CFG_PI_DFE_EN_SET(x)\
FIELD_PREP(SD10G_LANE_LANE_1A_CFG_PI_DFE_EN, x)
#define SD10G_LANE_LANE_1A_CFG_PI_DFE_EN_GET(x)\
FIELD_GET(SD10G_LANE_LANE_1A_CFG_PI_DFE_EN, x)
#define SD10G_LANE_LANE_1A_CFG_PI_STEPS BIT(3)
#define SD10G_LANE_LANE_1A_CFG_PI_STEPS_SET(x)\
FIELD_PREP(SD10G_LANE_LANE_1A_CFG_PI_STEPS, x)
#define SD10G_LANE_LANE_1A_CFG_PI_STEPS_GET(x)\
FIELD_GET(SD10G_LANE_LANE_1A_CFG_PI_STEPS, x)
#define SD10G_LANE_LANE_1A_CFG_PI_FLOOP_STEPS_1_0 GENMASK(5, 4)
#define SD10G_LANE_LANE_1A_CFG_PI_FLOOP_STEPS_1_0_SET(x)\
FIELD_PREP(SD10G_LANE_LANE_1A_CFG_PI_FLOOP_STEPS_1_0, x)
#define SD10G_LANE_LANE_1A_CFG_PI_FLOOP_STEPS_1_0_GET(x)\
FIELD_GET(SD10G_LANE_LANE_1A_CFG_PI_FLOOP_STEPS_1_0, x)
/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_22 */
#define SD10G_LANE_LANE_22(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 136, 0, 1, 4)
#define SD10G_LANE_LANE_22_CFG_DFETAP_EN_5_1 GENMASK(4, 0)
#define SD10G_LANE_LANE_22_CFG_DFETAP_EN_5_1_SET(x)\
FIELD_PREP(SD10G_LANE_LANE_22_CFG_DFETAP_EN_5_1, x)
#define SD10G_LANE_LANE_22_CFG_DFETAP_EN_5_1_GET(x)\
FIELD_GET(SD10G_LANE_LANE_22_CFG_DFETAP_EN_5_1, x)
/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_23 */
#define SD10G_LANE_LANE_23(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 140, 0, 1, 4)
#define SD10G_LANE_LANE_23_CFG_DFE_PD BIT(0)
#define SD10G_LANE_LANE_23_CFG_DFE_PD_SET(x)\
FIELD_PREP(SD10G_LANE_LANE_23_CFG_DFE_PD, x)
#define SD10G_LANE_LANE_23_CFG_DFE_PD_GET(x)\
FIELD_GET(SD10G_LANE_LANE_23_CFG_DFE_PD, x)
#define SD10G_LANE_LANE_23_CFG_EN_DFEDIG BIT(1)
#define SD10G_LANE_LANE_23_CFG_EN_DFEDIG_SET(x)\
FIELD_PREP(SD10G_LANE_LANE_23_CFG_EN_DFEDIG, x)
#define SD10G_LANE_LANE_23_CFG_EN_DFEDIG_GET(x)\
FIELD_GET(SD10G_LANE_LANE_23_CFG_EN_DFEDIG, x)
#define SD10G_LANE_LANE_23_CFG_DFECK_EN BIT(2)
#define SD10G_LANE_LANE_23_CFG_DFECK_EN_SET(x)\
FIELD_PREP(SD10G_LANE_LANE_23_CFG_DFECK_EN, x)
#define SD10G_LANE_LANE_23_CFG_DFECK_EN_GET(x)\
FIELD_GET(SD10G_LANE_LANE_23_CFG_DFECK_EN, x)
#define SD10G_LANE_LANE_23_CFG_ERRAMP_PD BIT(3)
#define SD10G_LANE_LANE_23_CFG_ERRAMP_PD_SET(x)\
FIELD_PREP(SD10G_LANE_LANE_23_CFG_ERRAMP_PD, x)
#define SD10G_LANE_LANE_23_CFG_ERRAMP_PD_GET(x)\
FIELD_GET(SD10G_LANE_LANE_23_CFG_ERRAMP_PD, x)
#define SD10G_LANE_LANE_23_CFG_DFEDIG_M_2_0 GENMASK(6, 4)
#define SD10G_LANE_LANE_23_CFG_DFEDIG_M_2_0_SET(x)\
FIELD_PREP(SD10G_LANE_LANE_23_CFG_DFEDIG_M_2_0, x)
#define SD10G_LANE_LANE_23_CFG_DFEDIG_M_2_0_GET(x)\
FIELD_GET(SD10G_LANE_LANE_23_CFG_DFEDIG_M_2_0, x)
/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_24 */
#define SD10G_LANE_LANE_24(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 144, 0, 1, 4)
#define SD10G_LANE_LANE_24_CFG_PI_BW_GEN1_3_0 GENMASK(3, 0)
#define SD10G_LANE_LANE_24_CFG_PI_BW_GEN1_3_0_SET(x)\
FIELD_PREP(SD10G_LANE_LANE_24_CFG_PI_BW_GEN1_3_0, x)
#define SD10G_LANE_LANE_24_CFG_PI_BW_GEN1_3_0_GET(x)\
FIELD_GET(SD10G_LANE_LANE_24_CFG_PI_BW_GEN1_3_0, x)
#define SD10G_LANE_LANE_24_CFG_PI_BW_GEN2_3_0 GENMASK(7, 4)
#define SD10G_LANE_LANE_24_CFG_PI_BW_GEN2_3_0_SET(x)\
FIELD_PREP(SD10G_LANE_LANE_24_CFG_PI_BW_GEN2_3_0, x)
#define SD10G_LANE_LANE_24_CFG_PI_BW_GEN2_3_0_GET(x)\
FIELD_GET(SD10G_LANE_LANE_24_CFG_PI_BW_GEN2_3_0, x)
/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_26 */
#define SD10G_LANE_LANE_26(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 152, 0, 1, 4)
#define SD10G_LANE_LANE_26_CFG_ISCAN_EXT_DAC_7_0 GENMASK(7, 0)
#define SD10G_LANE_LANE_26_CFG_ISCAN_EXT_DAC_7_0_SET(x)\
FIELD_PREP(SD10G_LANE_LANE_26_CFG_ISCAN_EXT_DAC_7_0, x)
#define SD10G_LANE_LANE_26_CFG_ISCAN_EXT_DAC_7_0_GET(x)\
FIELD_GET(SD10G_LANE_LANE_26_CFG_ISCAN_EXT_DAC_7_0, x)
/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_2F */
#define SD10G_LANE_LANE_2F(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 188, 0, 1, 4)
#define SD10G_LANE_LANE_2F_CFG_VGA_CP_2_0 GENMASK(2, 0)
#define SD10G_LANE_LANE_2F_CFG_VGA_CP_2_0_SET(x)\
FIELD_PREP(SD10G_LANE_LANE_2F_CFG_VGA_CP_2_0, x)
#define SD10G_LANE_LANE_2F_CFG_VGA_CP_2_0_GET(x)\
FIELD_GET(SD10G_LANE_LANE_2F_CFG_VGA_CP_2_0, x)
#define SD10G_LANE_LANE_2F_CFG_VGA_CTRL_3_0 GENMASK(7, 4)
#define SD10G_LANE_LANE_2F_CFG_VGA_CTRL_3_0_SET(x)\
FIELD_PREP(SD10G_LANE_LANE_2F_CFG_VGA_CTRL_3_0, x)
#define SD10G_LANE_LANE_2F_CFG_VGA_CTRL_3_0_GET(x)\
FIELD_GET(SD10G_LANE_LANE_2F_CFG_VGA_CTRL_3_0, x)
/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_30 */
#define SD10G_LANE_LANE_30(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 192, 0, 1, 4)
#define SD10G_LANE_LANE_30_CFG_SUMMER_EN BIT(0)
#define SD10G_LANE_LANE_30_CFG_SUMMER_EN_SET(x)\
FIELD_PREP(SD10G_LANE_LANE_30_CFG_SUMMER_EN, x)
#define SD10G_LANE_LANE_30_CFG_SUMMER_EN_GET(x)\
FIELD_GET(SD10G_LANE_LANE_30_CFG_SUMMER_EN, x)
#define SD10G_LANE_LANE_30_CFG_RXDIV_SEL_2_0 GENMASK(6, 4)
#define SD10G_LANE_LANE_30_CFG_RXDIV_SEL_2_0_SET(x)\
FIELD_PREP(SD10G_LANE_LANE_30_CFG_RXDIV_SEL_2_0, x)
#define SD10G_LANE_LANE_30_CFG_RXDIV_SEL_2_0_GET(x)\
FIELD_GET(SD10G_LANE_LANE_30_CFG_RXDIV_SEL_2_0, x)
/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_31 */
#define SD10G_LANE_LANE_31(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 196, 0, 1, 4)
#define SD10G_LANE_LANE_31_CFG_PI_RSTN BIT(0)
#define SD10G_LANE_LANE_31_CFG_PI_RSTN_SET(x)\
FIELD_PREP(SD10G_LANE_LANE_31_CFG_PI_RSTN, x)
#define SD10G_LANE_LANE_31_CFG_PI_RSTN_GET(x)\
FIELD_GET(SD10G_LANE_LANE_31_CFG_PI_RSTN, x)
#define SD10G_LANE_LANE_31_CFG_CDR_RSTN BIT(1)
#define SD10G_LANE_LANE_31_CFG_CDR_RSTN_SET(x)\
FIELD_PREP(SD10G_LANE_LANE_31_CFG_CDR_RSTN, x)
#define SD10G_LANE_LANE_31_CFG_CDR_RSTN_GET(x)\
FIELD_GET(SD10G_LANE_LANE_31_CFG_CDR_RSTN, x)
#define SD10G_LANE_LANE_31_CFG_RSTN_DFEDIG BIT(2)
#define SD10G_LANE_LANE_31_CFG_RSTN_DFEDIG_SET(x)\
FIELD_PREP(SD10G_LANE_LANE_31_CFG_RSTN_DFEDIG, x)
#define SD10G_LANE_LANE_31_CFG_RSTN_DFEDIG_GET(x)\
FIELD_GET(SD10G_LANE_LANE_31_CFG_RSTN_DFEDIG, x)
#define SD10G_LANE_LANE_31_CFG_CTLE_RSTN BIT(3)
#define SD10G_LANE_LANE_31_CFG_CTLE_RSTN_SET(x)\
FIELD_PREP(SD10G_LANE_LANE_31_CFG_CTLE_RSTN, x)
#define SD10G_LANE_LANE_31_CFG_CTLE_RSTN_GET(x)\
FIELD_GET(SD10G_LANE_LANE_31_CFG_CTLE_RSTN, x)
#define SD10G_LANE_LANE_31_CFG_RSTN_DIV5_8 BIT(4)
#define SD10G_LANE_LANE_31_CFG_RSTN_DIV5_8_SET(x)\
FIELD_PREP(SD10G_LANE_LANE_31_CFG_RSTN_DIV5_8, x)
#define SD10G_LANE_LANE_31_CFG_RSTN_DIV5_8_GET(x)\
FIELD_GET(SD10G_LANE_LANE_31_CFG_RSTN_DIV5_8, x)
#define SD10G_LANE_LANE_31_CFG_R50_EN BIT(5)
#define SD10G_LANE_LANE_31_CFG_R50_EN_SET(x)\
FIELD_PREP(SD10G_LANE_LANE_31_CFG_R50_EN, x)
#define SD10G_LANE_LANE_31_CFG_R50_EN_GET(x)\
FIELD_GET(SD10G_LANE_LANE_31_CFG_R50_EN, x)
/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_32 */
#define SD10G_LANE_LANE_32(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 200, 0, 1, 4)
#define SD10G_LANE_LANE_32_CFG_ITX_IPCLK_BASE_1_0 GENMASK(1, 0)
#define SD10G_LANE_LANE_32_CFG_ITX_IPCLK_BASE_1_0_SET(x)\
FIELD_PREP(SD10G_LANE_LANE_32_CFG_ITX_IPCLK_BASE_1_0, x)
#define SD10G_LANE_LANE_32_CFG_ITX_IPCLK_BASE_1_0_GET(x)\
FIELD_GET(SD10G_LANE_LANE_32_CFG_ITX_IPCLK_BASE_1_0, x)
#define SD10G_LANE_LANE_32_CFG_ITX_IPCML_BASE_1_0 GENMASK(5, 4)
#define SD10G_LANE_LANE_32_CFG_ITX_IPCML_BASE_1_0_SET(x)\
FIELD_PREP(SD10G_LANE_LANE_32_CFG_ITX_IPCML_BASE_1_0, x)
#define SD10G_LANE_LANE_32_CFG_ITX_IPCML_BASE_1_0_GET(x)\
FIELD_GET(SD10G_LANE_LANE_32_CFG_ITX_IPCML_BASE_1_0, x)
/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_33 */
#define SD10G_LANE_LANE_33(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 204, 0, 1, 4)
#define SD10G_LANE_LANE_33_CFG_ITX_IPDRIVER_BASE_2_0 GENMASK(2, 0)
#define SD10G_LANE_LANE_33_CFG_ITX_IPDRIVER_BASE_2_0_SET(x)\
FIELD_PREP(SD10G_LANE_LANE_33_CFG_ITX_IPDRIVER_BASE_2_0, x)
#define SD10G_LANE_LANE_33_CFG_ITX_IPDRIVER_BASE_2_0_GET(x)\
FIELD_GET(SD10G_LANE_LANE_33_CFG_ITX_IPDRIVER_BASE_2_0, x)
#define SD10G_LANE_LANE_33_CFG_ITX_IPPREEMP_BASE_1_0 GENMASK(5, 4)
#define SD10G_LANE_LANE_33_CFG_ITX_IPPREEMP_BASE_1_0_SET(x)\
FIELD_PREP(SD10G_LANE_LANE_33_CFG_ITX_IPPREEMP_BASE_1_0, x)
#define SD10G_LANE_LANE_33_CFG_ITX_IPPREEMP_BASE_1_0_GET(x)\
FIELD_GET(SD10G_LANE_LANE_33_CFG_ITX_IPPREEMP_BASE_1_0, x)
/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_35 */
#define SD10G_LANE_LANE_35(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 212, 0, 1, 4)
#define SD10G_LANE_LANE_35_CFG_TXRATE_1_0 GENMASK(1, 0)
#define SD10G_LANE_LANE_35_CFG_TXRATE_1_0_SET(x)\
FIELD_PREP(SD10G_LANE_LANE_35_CFG_TXRATE_1_0, x)
#define SD10G_LANE_LANE_35_CFG_TXRATE_1_0_GET(x)\
FIELD_GET(SD10G_LANE_LANE_35_CFG_TXRATE_1_0, x)
#define SD10G_LANE_LANE_35_CFG_RXRATE_1_0 GENMASK(5, 4)
#define SD10G_LANE_LANE_35_CFG_RXRATE_1_0_SET(x)\
FIELD_PREP(SD10G_LANE_LANE_35_CFG_RXRATE_1_0, x)
#define SD10G_LANE_LANE_35_CFG_RXRATE_1_0_GET(x)\
FIELD_GET(SD10G_LANE_LANE_35_CFG_RXRATE_1_0, x)
/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_36 */
#define SD10G_LANE_LANE_36(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 216, 0, 1, 4)
#define SD10G_LANE_LANE_36_CFG_PREDRV_SLEWRATE_1_0 GENMASK(1, 0)
#define SD10G_LANE_LANE_36_CFG_PREDRV_SLEWRATE_1_0_SET(x)\
FIELD_PREP(SD10G_LANE_LANE_36_CFG_PREDRV_SLEWRATE_1_0, x)
#define SD10G_LANE_LANE_36_CFG_PREDRV_SLEWRATE_1_0_GET(x)\
FIELD_GET(SD10G_LANE_LANE_36_CFG_PREDRV_SLEWRATE_1_0, x)
#define SD10G_LANE_LANE_36_CFG_EID_LP BIT(4)
#define SD10G_LANE_LANE_36_CFG_EID_LP_SET(x)\
FIELD_PREP(SD10G_LANE_LANE_36_CFG_EID_LP, x)
#define SD10G_LANE_LANE_36_CFG_EID_LP_GET(x)\
FIELD_GET(SD10G_LANE_LANE_36_CFG_EID_LP, x)
#define SD10G_LANE_LANE_36_CFG_EN_PREDRV_EMPH BIT(5)
#define SD10G_LANE_LANE_36_CFG_EN_PREDRV_EMPH_SET(x)\
FIELD_PREP(SD10G_LANE_LANE_36_CFG_EN_PREDRV_EMPH, x)
#define SD10G_LANE_LANE_36_CFG_EN_PREDRV_EMPH_GET(x)\
FIELD_GET(SD10G_LANE_LANE_36_CFG_EN_PREDRV_EMPH, x)
#define SD10G_LANE_LANE_36_CFG_PRBS_SEL BIT(6)
#define SD10G_LANE_LANE_36_CFG_PRBS_SEL_SET(x)\
FIELD_PREP(SD10G_LANE_LANE_36_CFG_PRBS_SEL, x)
#define SD10G_LANE_LANE_36_CFG_PRBS_SEL_GET(x)\
FIELD_GET(SD10G_LANE_LANE_36_CFG_PRBS_SEL, x)
#define SD10G_LANE_LANE_36_CFG_PRBS_SETB BIT(7)
#define SD10G_LANE_LANE_36_CFG_PRBS_SETB_SET(x)\
FIELD_PREP(SD10G_LANE_LANE_36_CFG_PRBS_SETB, x)
#define SD10G_LANE_LANE_36_CFG_PRBS_SETB_GET(x)\
FIELD_GET(SD10G_LANE_LANE_36_CFG_PRBS_SETB, x)
/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_37 */
#define SD10G_LANE_LANE_37(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 220, 0, 1, 4)
#define SD10G_LANE_LANE_37_CFG_RXDET_COMP_PD BIT(0)
#define SD10G_LANE_LANE_37_CFG_RXDET_COMP_PD_SET(x)\
FIELD_PREP(SD10G_LANE_LANE_37_CFG_RXDET_COMP_PD, x)
#define SD10G_LANE_LANE_37_CFG_RXDET_COMP_PD_GET(x)\
FIELD_GET(SD10G_LANE_LANE_37_CFG_RXDET_COMP_PD, x)
#define SD10G_LANE_LANE_37_CFG_PD_RX_CKTREE BIT(1)
#define SD10G_LANE_LANE_37_CFG_PD_RX_CKTREE_SET(x)\
FIELD_PREP(SD10G_LANE_LANE_37_CFG_PD_RX_CKTREE, x)
#define SD10G_LANE_LANE_37_CFG_PD_RX_CKTREE_GET(x)\
FIELD_GET(SD10G_LANE_LANE_37_CFG_PD_RX_CKTREE, x)
#define SD10G_LANE_LANE_37_CFG_TXSWING_HALF BIT(2)
#define SD10G_LANE_LANE_37_CFG_TXSWING_HALF_SET(x)\
FIELD_PREP(SD10G_LANE_LANE_37_CFG_TXSWING_HALF, x)
#define SD10G_LANE_LANE_37_CFG_TXSWING_HALF_GET(x)\
FIELD_GET(SD10G_LANE_LANE_37_CFG_TXSWING_HALF, x)
#define SD10G_LANE_LANE_37_CFG_IP_PRE_BASE_1_0 GENMASK(5, 4)
#define SD10G_LANE_LANE_37_CFG_IP_PRE_BASE_1_0_SET(x)\
FIELD_PREP(SD10G_LANE_LANE_37_CFG_IP_PRE_BASE_1_0, x)
#define SD10G_LANE_LANE_37_CFG_IP_PRE_BASE_1_0_GET(x)\
FIELD_GET(SD10G_LANE_LANE_37_CFG_IP_PRE_BASE_1_0, x)
/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_39 */
#define SD10G_LANE_LANE_39(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 228, 0, 1, 4)
#define SD10G_LANE_LANE_39_CFG_RXFILT_Y_2_0 GENMASK(2, 0)
#define SD10G_LANE_LANE_39_CFG_RXFILT_Y_2_0_SET(x)\
FIELD_PREP(SD10G_LANE_LANE_39_CFG_RXFILT_Y_2_0, x)
#define SD10G_LANE_LANE_39_CFG_RXFILT_Y_2_0_GET(x)\
FIELD_GET(SD10G_LANE_LANE_39_CFG_RXFILT_Y_2_0, x)
#define SD10G_LANE_LANE_39_CFG_RX_SSC_LH BIT(4)
#define SD10G_LANE_LANE_39_CFG_RX_SSC_LH_SET(x)\
FIELD_PREP(SD10G_LANE_LANE_39_CFG_RX_SSC_LH, x)
#define SD10G_LANE_LANE_39_CFG_RX_SSC_LH_GET(x)\
FIELD_GET(SD10G_LANE_LANE_39_CFG_RX_SSC_LH, x)
/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_3A */
#define SD10G_LANE_LANE_3A(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 232, 0, 1, 4)
#define SD10G_LANE_LANE_3A_CFG_MP_MIN_3_0 GENMASK(3, 0)
#define SD10G_LANE_LANE_3A_CFG_MP_MIN_3_0_SET(x)\
FIELD_PREP(SD10G_LANE_LANE_3A_CFG_MP_MIN_3_0, x)
#define SD10G_LANE_LANE_3A_CFG_MP_MIN_3_0_GET(x)\
FIELD_GET(SD10G_LANE_LANE_3A_CFG_MP_MIN_3_0, x)
#define SD10G_LANE_LANE_3A_CFG_MP_MAX_3_0 GENMASK(7, 4)
#define SD10G_LANE_LANE_3A_CFG_MP_MAX_3_0_SET(x)\
FIELD_PREP(SD10G_LANE_LANE_3A_CFG_MP_MAX_3_0, x)
#define SD10G_LANE_LANE_3A_CFG_MP_MAX_3_0_GET(x)\
FIELD_GET(SD10G_LANE_LANE_3A_CFG_MP_MAX_3_0, x)
/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_3C */
#define SD10G_LANE_LANE_3C(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 240, 0, 1, 4)
#define SD10G_LANE_LANE_3C_CFG_DIS_ACC BIT(0)
#define SD10G_LANE_LANE_3C_CFG_DIS_ACC_SET(x)\
FIELD_PREP(SD10G_LANE_LANE_3C_CFG_DIS_ACC, x)
#define SD10G_LANE_LANE_3C_CFG_DIS_ACC_GET(x)\
FIELD_GET(SD10G_LANE_LANE_3C_CFG_DIS_ACC, x)
#define SD10G_LANE_LANE_3C_CFG_DIS_2NDORDER BIT(1)
#define SD10G_LANE_LANE_3C_CFG_DIS_2NDORDER_SET(x)\
FIELD_PREP(SD10G_LANE_LANE_3C_CFG_DIS_2NDORDER, x)
#define SD10G_LANE_LANE_3C_CFG_DIS_2NDORDER_GET(x)\
FIELD_GET(SD10G_LANE_LANE_3C_CFG_DIS_2NDORDER, x)
/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_40 */
#define SD10G_LANE_LANE_40(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 256, 0, 1, 4)
#define SD10G_LANE_LANE_40_CFG_LANE_RESERVE_7_0 GENMASK(7, 0)
#define SD10G_LANE_LANE_40_CFG_LANE_RESERVE_7_0_SET(x)\
FIELD_PREP(SD10G_LANE_LANE_40_CFG_LANE_RESERVE_7_0, x)
#define SD10G_LANE_LANE_40_CFG_LANE_RESERVE_7_0_GET(x)\
FIELD_GET(SD10G_LANE_LANE_40_CFG_LANE_RESERVE_7_0, x)
/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_41 */
#define SD10G_LANE_LANE_41(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 260, 0, 1, 4)
#define SD10G_LANE_LANE_41_CFG_LANE_RESERVE_15_8 GENMASK(7, 0)
#define SD10G_LANE_LANE_41_CFG_LANE_RESERVE_15_8_SET(x)\
FIELD_PREP(SD10G_LANE_LANE_41_CFG_LANE_RESERVE_15_8, x)
#define SD10G_LANE_LANE_41_CFG_LANE_RESERVE_15_8_GET(x)\
FIELD_GET(SD10G_LANE_LANE_41_CFG_LANE_RESERVE_15_8, x)
/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_42 */
#define SD10G_LANE_LANE_42(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 264, 0, 1, 4)
#define SD10G_LANE_LANE_42_CFG_CDR_KF_GEN1_2_0 GENMASK(2, 0)
#define SD10G_LANE_LANE_42_CFG_CDR_KF_GEN1_2_0_SET(x)\
FIELD_PREP(SD10G_LANE_LANE_42_CFG_CDR_KF_GEN1_2_0, x)
#define SD10G_LANE_LANE_42_CFG_CDR_KF_GEN1_2_0_GET(x)\
FIELD_GET(SD10G_LANE_LANE_42_CFG_CDR_KF_GEN1_2_0, x)
#define SD10G_LANE_LANE_42_CFG_CDR_KF_GEN2_2_0 GENMASK(6, 4)
#define SD10G_LANE_LANE_42_CFG_CDR_KF_GEN2_2_0_SET(x)\
FIELD_PREP(SD10G_LANE_LANE_42_CFG_CDR_KF_GEN2_2_0, x)
#define SD10G_LANE_LANE_42_CFG_CDR_KF_GEN2_2_0_GET(x)\
FIELD_GET(SD10G_LANE_LANE_42_CFG_CDR_KF_GEN2_2_0, x)
/* SD10G_LANE_TARGET:LANE_GRP_1:LANE_48 */
#define SD10G_LANE_LANE_48(t) __REG(TARGET_SD10G_LANE, t, 12, 288, 0, 1, 40, 0, 0, 1, 4)
#define SD10G_LANE_LANE_48_CFG_ALOS_THR_3_0 GENMASK(3, 0)
#define SD10G_LANE_LANE_48_CFG_ALOS_THR_3_0_SET(x)\
FIELD_PREP(SD10G_LANE_LANE_48_CFG_ALOS_THR_3_0, x)
#define SD10G_LANE_LANE_48_CFG_ALOS_THR_3_0_GET(x)\
FIELD_GET(SD10G_LANE_LANE_48_CFG_ALOS_THR_3_0, x)
#define SD10G_LANE_LANE_48_CFG_AUX_RXCK_SEL BIT(4)
#define SD10G_LANE_LANE_48_CFG_AUX_RXCK_SEL_SET(x)\
FIELD_PREP(SD10G_LANE_LANE_48_CFG_AUX_RXCK_SEL, x)
#define SD10G_LANE_LANE_48_CFG_AUX_RXCK_SEL_GET(x)\
FIELD_GET(SD10G_LANE_LANE_48_CFG_AUX_RXCK_SEL, x)
#define SD10G_LANE_LANE_48_CFG_CLK_ENQ BIT(5)
#define SD10G_LANE_LANE_48_CFG_CLK_ENQ_SET(x)\
FIELD_PREP(SD10G_LANE_LANE_48_CFG_CLK_ENQ, x)
#define SD10G_LANE_LANE_48_CFG_CLK_ENQ_GET(x)\
FIELD_GET(SD10G_LANE_LANE_48_CFG_CLK_ENQ, x)
/* SD10G_LANE_TARGET:LANE_GRP_1:LANE_50 */
#define SD10G_LANE_LANE_50(t) __REG(TARGET_SD10G_LANE, t, 12, 288, 0, 1, 40, 32, 0, 1, 4)
#define SD10G_LANE_LANE_50_CFG_SSC_PI_STEP_1_0 GENMASK(1, 0)
#define SD10G_LANE_LANE_50_CFG_SSC_PI_STEP_1_0_SET(x)\
FIELD_PREP(SD10G_LANE_LANE_50_CFG_SSC_PI_STEP_1_0, x)
#define SD10G_LANE_LANE_50_CFG_SSC_PI_STEP_1_0_GET(x)\
FIELD_GET(SD10G_LANE_LANE_50_CFG_SSC_PI_STEP_1_0, x)
#define SD10G_LANE_LANE_50_CFG_SSC_RESETB BIT(4)
#define SD10G_LANE_LANE_50_CFG_SSC_RESETB_SET(x)\
FIELD_PREP(SD10G_LANE_LANE_50_CFG_SSC_RESETB, x)
#define SD10G_LANE_LANE_50_CFG_SSC_RESETB_GET(x)\
FIELD_GET(SD10G_LANE_LANE_50_CFG_SSC_RESETB, x)
#define SD10G_LANE_LANE_50_CFG_SSC_RTL_CLK_SEL BIT(5)
#define SD10G_LANE_LANE_50_CFG_SSC_RTL_CLK_SEL_SET(x)\
FIELD_PREP(SD10G_LANE_LANE_50_CFG_SSC_RTL_CLK_SEL, x)
#define SD10G_LANE_LANE_50_CFG_SSC_RTL_CLK_SEL_GET(x)\
FIELD_GET(SD10G_LANE_LANE_50_CFG_SSC_RTL_CLK_SEL, x)
#define SD10G_LANE_LANE_50_CFG_AUX_TXCK_SEL BIT(6)
#define SD10G_LANE_LANE_50_CFG_AUX_TXCK_SEL_SET(x)\
FIELD_PREP(SD10G_LANE_LANE_50_CFG_AUX_TXCK_SEL, x)
#define SD10G_LANE_LANE_50_CFG_AUX_TXCK_SEL_GET(x)\
FIELD_GET(SD10G_LANE_LANE_50_CFG_AUX_TXCK_SEL, x)
#define SD10G_LANE_LANE_50_CFG_JT_EN BIT(7)
#define SD10G_LANE_LANE_50_CFG_JT_EN_SET(x)\
FIELD_PREP(SD10G_LANE_LANE_50_CFG_JT_EN, x)
#define SD10G_LANE_LANE_50_CFG_JT_EN_GET(x)\
FIELD_GET(SD10G_LANE_LANE_50_CFG_JT_EN, x)
/* SD10G_LANE_TARGET:LANE_GRP_2:LANE_52 */
#define SD10G_LANE_LANE_52(t) __REG(TARGET_SD10G_LANE, t, 12, 328, 0, 1, 24, 0, 0, 1, 4)
#define SD10G_LANE_LANE_52_CFG_IBIAS_TUNE_RESERVE_5_0 GENMASK(5, 0)
#define SD10G_LANE_LANE_52_CFG_IBIAS_TUNE_RESERVE_5_0_SET(x)\
FIELD_PREP(SD10G_LANE_LANE_52_CFG_IBIAS_TUNE_RESERVE_5_0, x)
#define SD10G_LANE_LANE_52_CFG_IBIAS_TUNE_RESERVE_5_0_GET(x)\
FIELD_GET(SD10G_LANE_LANE_52_CFG_IBIAS_TUNE_RESERVE_5_0, x)
/* SD10G_LANE_TARGET:LANE_GRP_4:LANE_83 */
#define SD10G_LANE_LANE_83(t) __REG(TARGET_SD10G_LANE, t, 12, 464, 0, 1, 112, 60, 0, 1, 4)
#define SD10G_LANE_LANE_83_R_TX_BIT_REVERSE BIT(0)
#define SD10G_LANE_LANE_83_R_TX_BIT_REVERSE_SET(x)\
FIELD_PREP(SD10G_LANE_LANE_83_R_TX_BIT_REVERSE, x)
#define SD10G_LANE_LANE_83_R_TX_BIT_REVERSE_GET(x)\
FIELD_GET(SD10G_LANE_LANE_83_R_TX_BIT_REVERSE, x)
#define SD10G_LANE_LANE_83_R_TX_POL_INV BIT(1)
#define SD10G_LANE_LANE_83_R_TX_POL_INV_SET(x)\
FIELD_PREP(SD10G_LANE_LANE_83_R_TX_POL_INV, x)
#define SD10G_LANE_LANE_83_R_TX_POL_INV_GET(x)\
FIELD_GET(SD10G_LANE_LANE_83_R_TX_POL_INV, x)
#define SD10G_LANE_LANE_83_R_RX_BIT_REVERSE BIT(2)
#define SD10G_LANE_LANE_83_R_RX_BIT_REVERSE_SET(x)\
FIELD_PREP(SD10G_LANE_LANE_83_R_RX_BIT_REVERSE, x)
#define SD10G_LANE_LANE_83_R_RX_BIT_REVERSE_GET(x)\
FIELD_GET(SD10G_LANE_LANE_83_R_RX_BIT_REVERSE, x)
#define SD10G_LANE_LANE_83_R_RX_POL_INV BIT(3)
#define SD10G_LANE_LANE_83_R_RX_POL_INV_SET(x)\
FIELD_PREP(SD10G_LANE_LANE_83_R_RX_POL_INV, x)
#define SD10G_LANE_LANE_83_R_RX_POL_INV_GET(x)\
FIELD_GET(SD10G_LANE_LANE_83_R_RX_POL_INV, x)
#define SD10G_LANE_LANE_83_R_DFE_RSTN BIT(4)
#define SD10G_LANE_LANE_83_R_DFE_RSTN_SET(x)\
FIELD_PREP(SD10G_LANE_LANE_83_R_DFE_RSTN, x)
#define SD10G_LANE_LANE_83_R_DFE_RSTN_GET(x)\
FIELD_GET(SD10G_LANE_LANE_83_R_DFE_RSTN, x)
#define SD10G_LANE_LANE_83_R_CDR_RSTN BIT(5)
#define SD10G_LANE_LANE_83_R_CDR_RSTN_SET(x)\
FIELD_PREP(SD10G_LANE_LANE_83_R_CDR_RSTN, x)
#define SD10G_LANE_LANE_83_R_CDR_RSTN_GET(x)\
FIELD_GET(SD10G_LANE_LANE_83_R_CDR_RSTN, x)
#define SD10G_LANE_LANE_83_R_CTLE_RSTN BIT(6)
#define SD10G_LANE_LANE_83_R_CTLE_RSTN_SET(x)\
FIELD_PREP(SD10G_LANE_LANE_83_R_CTLE_RSTN, x)
#define SD10G_LANE_LANE_83_R_CTLE_RSTN_GET(x)\
FIELD_GET(SD10G_LANE_LANE_83_R_CTLE_RSTN, x)
/* SD10G_LANE_TARGET:LANE_GRP_5:LANE_93 */
#define SD10G_LANE_LANE_93(t) __REG(TARGET_SD10G_LANE, t, 12, 576, 0, 1, 64, 12, 0, 1, 4)
#define SD10G_LANE_LANE_93_R_RXEI_FIFO_RST_EN BIT(0)
#define SD10G_LANE_LANE_93_R_RXEI_FIFO_RST_EN_SET(x)\
FIELD_PREP(SD10G_LANE_LANE_93_R_RXEI_FIFO_RST_EN, x)
#define SD10G_LANE_LANE_93_R_RXEI_FIFO_RST_EN_GET(x)\
FIELD_GET(SD10G_LANE_LANE_93_R_RXEI_FIFO_RST_EN, x)
#define SD10G_LANE_LANE_93_R_DWIDTHCTRL_FROM_HWT BIT(1)
#define SD10G_LANE_LANE_93_R_DWIDTHCTRL_FROM_HWT_SET(x)\
FIELD_PREP(SD10G_LANE_LANE_93_R_DWIDTHCTRL_FROM_HWT, x)
#define SD10G_LANE_LANE_93_R_DWIDTHCTRL_FROM_HWT_GET(x)\
FIELD_GET(SD10G_LANE_LANE_93_R_DWIDTHCTRL_FROM_HWT, x)
#define SD10G_LANE_LANE_93_R_DIS_RESTORE_DFE BIT(2)
#define SD10G_LANE_LANE_93_R_DIS_RESTORE_DFE_SET(x)\
FIELD_PREP(SD10G_LANE_LANE_93_R_DIS_RESTORE_DFE, x)
#define SD10G_LANE_LANE_93_R_DIS_RESTORE_DFE_GET(x)\
FIELD_GET(SD10G_LANE_LANE_93_R_DIS_RESTORE_DFE, x)
#define SD10G_LANE_LANE_93_R_EN_RATECHG_CTRL BIT(3)
#define SD10G_LANE_LANE_93_R_EN_RATECHG_CTRL_SET(x)\
FIELD_PREP(SD10G_LANE_LANE_93_R_EN_RATECHG_CTRL, x)
#define SD10G_LANE_LANE_93_R_EN_RATECHG_CTRL_GET(x)\
FIELD_GET(SD10G_LANE_LANE_93_R_EN_RATECHG_CTRL, x)
#define SD10G_LANE_LANE_93_R_REG_MANUAL BIT(4)
#define SD10G_LANE_LANE_93_R_REG_MANUAL_SET(x)\
FIELD_PREP(SD10G_LANE_LANE_93_R_REG_MANUAL, x)
#define SD10G_LANE_LANE_93_R_REG_MANUAL_GET(x)\
FIELD_GET(SD10G_LANE_LANE_93_R_REG_MANUAL, x)
#define SD10G_LANE_LANE_93_R_AUXCKSEL_FROM_HWT BIT(5)
#define SD10G_LANE_LANE_93_R_AUXCKSEL_FROM_HWT_SET(x)\
FIELD_PREP(SD10G_LANE_LANE_93_R_AUXCKSEL_FROM_HWT, x)
#define SD10G_LANE_LANE_93_R_AUXCKSEL_FROM_HWT_GET(x)\
FIELD_GET(SD10G_LANE_LANE_93_R_AUXCKSEL_FROM_HWT, x)
#define SD10G_LANE_LANE_93_R_LANE_ID_FROM_HWT BIT(6)
#define SD10G_LANE_LANE_93_R_LANE_ID_FROM_HWT_SET(x)\
FIELD_PREP(SD10G_LANE_LANE_93_R_LANE_ID_FROM_HWT, x)
#define SD10G_LANE_LANE_93_R_LANE_ID_FROM_HWT_GET(x)\
FIELD_GET(SD10G_LANE_LANE_93_R_LANE_ID_FROM_HWT, x)
#define SD10G_LANE_LANE_93_R_RX_PCIE_GEN12_FROM_HWT BIT(7)
#define SD10G_LANE_LANE_93_R_RX_PCIE_GEN12_FROM_HWT_SET(x)\
FIELD_PREP(SD10G_LANE_LANE_93_R_RX_PCIE_GEN12_FROM_HWT, x)
#define SD10G_LANE_LANE_93_R_RX_PCIE_GEN12_FROM_HWT_GET(x)\
FIELD_GET(SD10G_LANE_LANE_93_R_RX_PCIE_GEN12_FROM_HWT, x)
/* SD10G_LANE_TARGET:LANE_GRP_5:LANE_94 */
#define SD10G_LANE_LANE_94(t) __REG(TARGET_SD10G_LANE, t, 12, 576, 0, 1, 64, 16, 0, 1, 4)
#define SD10G_LANE_LANE_94_R_DWIDTHCTRL_2_0 GENMASK(2, 0)
#define SD10G_LANE_LANE_94_R_DWIDTHCTRL_2_0_SET(x)\
FIELD_PREP(SD10G_LANE_LANE_94_R_DWIDTHCTRL_2_0, x)
#define SD10G_LANE_LANE_94_R_DWIDTHCTRL_2_0_GET(x)\
FIELD_GET(SD10G_LANE_LANE_94_R_DWIDTHCTRL_2_0, x)
#define SD10G_LANE_LANE_94_R_ISCAN_REG BIT(4)
#define SD10G_LANE_LANE_94_R_ISCAN_REG_SET(x)\
FIELD_PREP(SD10G_LANE_LANE_94_R_ISCAN_REG, x)
#define SD10G_LANE_LANE_94_R_ISCAN_REG_GET(x)\
FIELD_GET(SD10G_LANE_LANE_94_R_ISCAN_REG, x)
#define SD10G_LANE_LANE_94_R_TXEQ_REG BIT(5)
#define SD10G_LANE_LANE_94_R_TXEQ_REG_SET(x)\
FIELD_PREP(SD10G_LANE_LANE_94_R_TXEQ_REG, x)
#define SD10G_LANE_LANE_94_R_TXEQ_REG_GET(x)\
FIELD_GET(SD10G_LANE_LANE_94_R_TXEQ_REG, x)
#define SD10G_LANE_LANE_94_R_MISC_REG BIT(6)
#define SD10G_LANE_LANE_94_R_MISC_REG_SET(x)\
FIELD_PREP(SD10G_LANE_LANE_94_R_MISC_REG, x)
#define SD10G_LANE_LANE_94_R_MISC_REG_GET(x)\
FIELD_GET(SD10G_LANE_LANE_94_R_MISC_REG, x)
#define SD10G_LANE_LANE_94_R_SWING_REG BIT(7)
#define SD10G_LANE_LANE_94_R_SWING_REG_SET(x)\
FIELD_PREP(SD10G_LANE_LANE_94_R_SWING_REG, x)
#define SD10G_LANE_LANE_94_R_SWING_REG_GET(x)\
FIELD_GET(SD10G_LANE_LANE_94_R_SWING_REG, x)
/* SD10G_LANE_TARGET:LANE_GRP_5:LANE_9E */
#define SD10G_LANE_LANE_9E(t) __REG(TARGET_SD10G_LANE, t, 12, 576, 0, 1, 64, 56, 0, 1, 4)
#define SD10G_LANE_LANE_9E_R_RXEQ_REG BIT(0)
#define SD10G_LANE_LANE_9E_R_RXEQ_REG_SET(x)\
FIELD_PREP(SD10G_LANE_LANE_9E_R_RXEQ_REG, x)
#define SD10G_LANE_LANE_9E_R_RXEQ_REG_GET(x)\
FIELD_GET(SD10G_LANE_LANE_9E_R_RXEQ_REG, x)
#define SD10G_LANE_LANE_9E_R_AUTO_RST_TREE_PD_MAN BIT(1)
#define SD10G_LANE_LANE_9E_R_AUTO_RST_TREE_PD_MAN_SET(x)\
FIELD_PREP(SD10G_LANE_LANE_9E_R_AUTO_RST_TREE_PD_MAN, x)
#define SD10G_LANE_LANE_9E_R_AUTO_RST_TREE_PD_MAN_GET(x)\
FIELD_GET(SD10G_LANE_LANE_9E_R_AUTO_RST_TREE_PD_MAN, x)
#define SD10G_LANE_LANE_9E_R_EN_AUTO_CDR_RSTN BIT(2)
#define SD10G_LANE_LANE_9E_R_EN_AUTO_CDR_RSTN_SET(x)\
FIELD_PREP(SD10G_LANE_LANE_9E_R_EN_AUTO_CDR_RSTN, x)
#define SD10G_LANE_LANE_9E_R_EN_AUTO_CDR_RSTN_GET(x)\
FIELD_GET(SD10G_LANE_LANE_9E_R_EN_AUTO_CDR_RSTN, x)
/* SD10G_LANE_TARGET:LANE_GRP_6:LANE_A1 */
#define SD10G_LANE_LANE_A1(t) __REG(TARGET_SD10G_LANE, t, 12, 640, 0, 1, 128, 4, 0, 1, 4)
#define SD10G_LANE_LANE_A1_R_PMA_TXCK_DIV_SEL_1_0 GENMASK(1, 0)
#define SD10G_LANE_LANE_A1_R_PMA_TXCK_DIV_SEL_1_0_SET(x)\
FIELD_PREP(SD10G_LANE_LANE_A1_R_PMA_TXCK_DIV_SEL_1_0, x)
#define SD10G_LANE_LANE_A1_R_PMA_TXCK_DIV_SEL_1_0_GET(x)\
FIELD_GET(SD10G_LANE_LANE_A1_R_PMA_TXCK_DIV_SEL_1_0, x)
#define SD10G_LANE_LANE_A1_R_SSC_FROM_HWT BIT(4)
#define SD10G_LANE_LANE_A1_R_SSC_FROM_HWT_SET(x)\
FIELD_PREP(SD10G_LANE_LANE_A1_R_SSC_FROM_HWT, x)
#define SD10G_LANE_LANE_A1_R_SSC_FROM_HWT_GET(x)\
FIELD_GET(SD10G_LANE_LANE_A1_R_SSC_FROM_HWT, x)
#define SD10G_LANE_LANE_A1_R_CDR_FROM_HWT BIT(5)
#define SD10G_LANE_LANE_A1_R_CDR_FROM_HWT_SET(x)\
FIELD_PREP(SD10G_LANE_LANE_A1_R_CDR_FROM_HWT, x)
#define SD10G_LANE_LANE_A1_R_CDR_FROM_HWT_GET(x)\
FIELD_GET(SD10G_LANE_LANE_A1_R_CDR_FROM_HWT, x)
#define SD10G_LANE_LANE_A1_R_PCLK_GATING_FROM_HWT BIT(6)
#define SD10G_LANE_LANE_A1_R_PCLK_GATING_FROM_HWT_SET(x)\
FIELD_PREP(SD10G_LANE_LANE_A1_R_PCLK_GATING_FROM_HWT, x)
#define SD10G_LANE_LANE_A1_R_PCLK_GATING_FROM_HWT_GET(x)\
FIELD_GET(SD10G_LANE_LANE_A1_R_PCLK_GATING_FROM_HWT, x)
#define SD10G_LANE_LANE_A1_R_PCLK_GATING BIT(7)
#define SD10G_LANE_LANE_A1_R_PCLK_GATING_SET(x)\
FIELD_PREP(SD10G_LANE_LANE_A1_R_PCLK_GATING, x)
#define SD10G_LANE_LANE_A1_R_PCLK_GATING_GET(x)\
FIELD_GET(SD10G_LANE_LANE_A1_R_PCLK_GATING, x)
/* SD10G_LANE_TARGET:LANE_GRP_6:LANE_A2 */
#define SD10G_LANE_LANE_A2(t) __REG(TARGET_SD10G_LANE, t, 12, 640, 0, 1, 128, 8, 0, 1, 4)
#define SD10G_LANE_LANE_A2_R_PCS2PMA_PHYMODE_4_0 GENMASK(4, 0)
#define SD10G_LANE_LANE_A2_R_PCS2PMA_PHYMODE_4_0_SET(x)\
FIELD_PREP(SD10G_LANE_LANE_A2_R_PCS2PMA_PHYMODE_4_0, x)
#define SD10G_LANE_LANE_A2_R_PCS2PMA_PHYMODE_4_0_GET(x)\
FIELD_GET(SD10G_LANE_LANE_A2_R_PCS2PMA_PHYMODE_4_0, x)
/* SD10G_LANE_TARGET:LANE_GRP_8:LANE_DF */
#define SD10G_LANE_LANE_DF(t) __REG(TARGET_SD10G_LANE, t, 12, 832, 0, 1, 84, 60, 0, 1, 4)
#define SD10G_LANE_LANE_DF_LOL_UDL BIT(0)
#define SD10G_LANE_LANE_DF_LOL_UDL_SET(x)\
FIELD_PREP(SD10G_LANE_LANE_DF_LOL_UDL, x)
#define SD10G_LANE_LANE_DF_LOL_UDL_GET(x)\
FIELD_GET(SD10G_LANE_LANE_DF_LOL_UDL, x)
#define SD10G_LANE_LANE_DF_LOL BIT(1)
#define SD10G_LANE_LANE_DF_LOL_SET(x)\
FIELD_PREP(SD10G_LANE_LANE_DF_LOL, x)
#define SD10G_LANE_LANE_DF_LOL_GET(x)\
FIELD_GET(SD10G_LANE_LANE_DF_LOL, x)
#define SD10G_LANE_LANE_DF_PMA2PCS_RXEI_FILTERED BIT(2)
#define SD10G_LANE_LANE_DF_PMA2PCS_RXEI_FILTERED_SET(x)\
FIELD_PREP(SD10G_LANE_LANE_DF_PMA2PCS_RXEI_FILTERED, x)
#define SD10G_LANE_LANE_DF_PMA2PCS_RXEI_FILTERED_GET(x)\
FIELD_GET(SD10G_LANE_LANE_DF_PMA2PCS_RXEI_FILTERED, x)
#define SD10G_LANE_LANE_DF_SQUELCH BIT(3)
#define SD10G_LANE_LANE_DF_SQUELCH_SET(x)\
FIELD_PREP(SD10G_LANE_LANE_DF_SQUELCH, x)
#define SD10G_LANE_LANE_DF_SQUELCH_GET(x)\
FIELD_GET(SD10G_LANE_LANE_DF_SQUELCH, x)
/* SD25G_TARGET:CMU_GRP_0:CMU_09 */
#define SD25G_LANE_CMU_09(t) __REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 36, 0, 1, 4)
#define SD25G_LANE_CMU_09_CFG_REFCK_TERM_EN BIT(0)
#define SD25G_LANE_CMU_09_CFG_REFCK_TERM_EN_SET(x)\
FIELD_PREP(SD25G_LANE_CMU_09_CFG_REFCK_TERM_EN, x)
#define SD25G_LANE_CMU_09_CFG_REFCK_TERM_EN_GET(x)\
FIELD_GET(SD25G_LANE_CMU_09_CFG_REFCK_TERM_EN, x)
#define SD25G_LANE_CMU_09_CFG_EN_DUMMY BIT(1)
#define SD25G_LANE_CMU_09_CFG_EN_DUMMY_SET(x)\
FIELD_PREP(SD25G_LANE_CMU_09_CFG_EN_DUMMY, x)
#define SD25G_LANE_CMU_09_CFG_EN_DUMMY_GET(x)\
FIELD_GET(SD25G_LANE_CMU_09_CFG_EN_DUMMY, x)
#define SD25G_LANE_CMU_09_CFG_PLL_LOS_SET BIT(2)
#define SD25G_LANE_CMU_09_CFG_PLL_LOS_SET_SET(x)\
FIELD_PREP(SD25G_LANE_CMU_09_CFG_PLL_LOS_SET, x)
#define SD25G_LANE_CMU_09_CFG_PLL_LOS_SET_GET(x)\
FIELD_GET(SD25G_LANE_CMU_09_CFG_PLL_LOS_SET, x)
#define SD25G_LANE_CMU_09_CFG_CTRL_LOGIC_PD BIT(3)
#define SD25G_LANE_CMU_09_CFG_CTRL_LOGIC_PD_SET(x)\
FIELD_PREP(SD25G_LANE_CMU_09_CFG_CTRL_LOGIC_PD, x)
#define SD25G_LANE_CMU_09_CFG_CTRL_LOGIC_PD_GET(x)\
FIELD_GET(SD25G_LANE_CMU_09_CFG_CTRL_LOGIC_PD, x)
#define SD25G_LANE_CMU_09_CFG_PLL_TP_SEL_1_0 GENMASK(5, 4)
#define SD25G_LANE_CMU_09_CFG_PLL_TP_SEL_1_0_SET(x)\
FIELD_PREP(SD25G_LANE_CMU_09_CFG_PLL_TP_SEL_1_0, x)
#define SD25G_LANE_CMU_09_CFG_PLL_TP_SEL_1_0_GET(x)\
FIELD_GET(SD25G_LANE_CMU_09_CFG_PLL_TP_SEL_1_0, x)
/* SD25G_TARGET:CMU_GRP_0:CMU_0B */
#define SD25G_LANE_CMU_0B(t) __REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 44, 0, 1, 4)
#define SD25G_LANE_CMU_0B_CFG_FORCE_RX_FILT BIT(0)
#define SD25G_LANE_CMU_0B_CFG_FORCE_RX_FILT_SET(x)\
FIELD_PREP(SD25G_LANE_CMU_0B_CFG_FORCE_RX_FILT, x)
#define SD25G_LANE_CMU_0B_CFG_FORCE_RX_FILT_GET(x)\
FIELD_GET(SD25G_LANE_CMU_0B_CFG_FORCE_RX_FILT, x)
#define SD25G_LANE_CMU_0B_CFG_DISLOL BIT(1)