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sparx5_serdes.c
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sparx5_serdes.c
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// SPDX-License-Identifier: GPL-2.0-or-later
/* Microchip Sparx5 Switch SerDes driver
*
* Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
*
* The Sparx5 Chip Register Model can be browsed at this location:
* https://github.com/microchip-ung/sparx-5_reginfo
* and the datasheet is available here:
* https://ww1.microchip.com/downloads/en/DeviceDoc/SparX-5_Family_L2L3_Enterprise_10G_Ethernet_Switches_Datasheet_00003822B.pdf
*/
#include <linux/printk.h>
#include <linux/module.h>
#include <linux/device.h>
#include <linux/netdevice.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include <linux/io.h>
#include <linux/clk.h>
#include <linux/phy.h>
#include <linux/phy/phy.h>
#include "sparx5_serdes.h"
#define SPX5_CMU_MAX 14
#define SPX5_SERDES_10G_START 13
#define SPX5_SERDES_25G_START 25
#define SPX5_SERDES_6G10G_CNT SPX5_SERDES_25G_START
/* Optimal power settings from GUC */
#define SPX5_SERDES_QUIET_MODE_VAL 0x01ef4e0c
enum sparx5_10g28cmu_mode {
SPX5_SD10G28_CMU_MAIN = 0,
SPX5_SD10G28_CMU_AUX1 = 1,
SPX5_SD10G28_CMU_AUX2 = 3,
SPX5_SD10G28_CMU_NONE = 4,
SPX5_SD10G28_CMU_MAX,
};
enum sparx5_sd25g28_mode_preset_type {
SPX5_SD25G28_MODE_PRESET_25000,
SPX5_SD25G28_MODE_PRESET_10000,
SPX5_SD25G28_MODE_PRESET_5000,
SPX5_SD25G28_MODE_PRESET_SD_2G5,
SPX5_SD25G28_MODE_PRESET_1000BASEX,
};
enum sparx5_sd10g28_mode_preset_type {
SPX5_SD10G28_MODE_PRESET_10000,
SPX5_SD10G28_MODE_PRESET_SFI_5000_6G,
SPX5_SD10G28_MODE_PRESET_SFI_5000_10G,
SPX5_SD10G28_MODE_PRESET_QSGMII,
SPX5_SD10G28_MODE_PRESET_SD_2G5,
SPX5_SD10G28_MODE_PRESET_1000BASEX,
};
struct sparx5_serdes_io_resource {
enum sparx5_serdes_target id;
phys_addr_t offset;
};
struct sparx5_sd25g28_mode_preset {
u8 bitwidth;
u8 tx_pre_div;
u8 fifo_ck_div;
u8 pre_divsel;
u8 vco_div_mode;
u8 sel_div;
u8 ck_bitwidth;
u8 subrate;
u8 com_txcal_en;
u8 com_tx_reserve_msb;
u8 com_tx_reserve_lsb;
u8 cfg_itx_ipcml_base;
u8 tx_reserve_lsb;
u8 tx_reserve_msb;
u8 bw;
u8 rxterm;
u8 dfe_tap;
u8 dfe_enable;
bool txmargin;
u8 cfg_ctle_rstn;
u8 r_dfe_rstn;
u8 cfg_pi_bw_3_0;
u8 tx_tap_dly;
u8 tx_tap_adv;
};
struct sparx5_sd25g28_media_preset {
u8 cfg_eq_c_force_3_0;
u8 cfg_vga_ctrl_byp_4_0;
u8 cfg_eq_r_force_3_0;
u8 cfg_en_adv;
u8 cfg_en_main;
u8 cfg_en_dly;
u8 cfg_tap_adv_3_0;
u8 cfg_tap_main;
u8 cfg_tap_dly_4_0;
u8 cfg_alos_thr_2_0;
};
struct sparx5_sd25g28_args {
u8 if_width; /* UDL if-width: 10/16/20/32/64 */
bool skip_cmu_cfg:1; /* Enable/disable CMU cfg */
enum sparx5_10g28cmu_mode cmu_sel; /* Device/Mode serdes uses */
bool no_pwrcycle:1; /* Omit initial power-cycle */
bool txinvert:1; /* Enable inversion of output data */
bool rxinvert:1; /* Enable inversion of input data */
u16 txswing; /* Set output level */
u8 rate; /* Rate of network interface */
u8 pi_bw_gen1;
u8 duty_cycle; /* Set output level to half/full */
bool mute:1; /* Mute Output Buffer */
bool reg_rst:1;
u8 com_pll_reserve;
};
struct sparx5_sd25g28_params {
u8 reg_rst;
u8 cfg_jc_byp;
u8 cfg_common_reserve_7_0;
u8 r_reg_manual;
u8 r_d_width_ctrl_from_hwt;
u8 r_d_width_ctrl_2_0;
u8 r_txfifo_ck_div_pmad_2_0;
u8 r_rxfifo_ck_div_pmad_2_0;
u8 cfg_pll_lol_set;
u8 cfg_vco_div_mode_1_0;
u8 cfg_pre_divsel_1_0;
u8 cfg_sel_div_3_0;
u8 cfg_vco_start_code_3_0;
u8 cfg_pma_tx_ck_bitwidth_2_0;
u8 cfg_tx_prediv_1_0;
u8 cfg_rxdiv_sel_2_0;
u8 cfg_tx_subrate_2_0;
u8 cfg_rx_subrate_2_0;
u8 r_multi_lane_mode;
u8 cfg_cdrck_en;
u8 cfg_dfeck_en;
u8 cfg_dfe_pd;
u8 cfg_dfedmx_pd;
u8 cfg_dfetap_en_5_1;
u8 cfg_dmux_pd;
u8 cfg_dmux_clk_pd;
u8 cfg_erramp_pd;
u8 cfg_pi_dfe_en;
u8 cfg_pi_en;
u8 cfg_pd_ctle;
u8 cfg_summer_en;
u8 cfg_pmad_ck_pd;
u8 cfg_pd_clk;
u8 cfg_pd_cml;
u8 cfg_pd_driver;
u8 cfg_rx_reg_pu;
u8 cfg_pd_rms_det;
u8 cfg_dcdr_pd;
u8 cfg_ecdr_pd;
u8 cfg_pd_sq;
u8 cfg_itx_ipdriver_base_2_0;
u8 cfg_tap_dly_4_0;
u8 cfg_tap_main;
u8 cfg_en_main;
u8 cfg_tap_adv_3_0;
u8 cfg_en_adv;
u8 cfg_en_dly;
u8 cfg_iscan_en;
u8 l1_pcs_en_fast_iscan;
u8 l0_cfg_bw_1_0;
u8 l0_cfg_txcal_en;
u8 cfg_en_dummy;
u8 cfg_pll_reserve_3_0;
u8 l0_cfg_tx_reserve_15_8;
u8 l0_cfg_tx_reserve_7_0;
u8 cfg_tx_reserve_15_8;
u8 cfg_tx_reserve_7_0;
u8 cfg_bw_1_0;
u8 cfg_txcal_man_en;
u8 cfg_phase_man_4_0;
u8 cfg_quad_man_1_0;
u8 cfg_txcal_shift_code_5_0;
u8 cfg_txcal_valid_sel_3_0;
u8 cfg_txcal_en;
u8 cfg_cdr_kf_2_0;
u8 cfg_cdr_m_7_0;
u8 cfg_pi_bw_3_0;
u8 cfg_pi_steps_1_0;
u8 cfg_dis_2ndorder;
u8 cfg_ctle_rstn;
u8 r_dfe_rstn;
u8 cfg_alos_thr_2_0;
u8 cfg_itx_ipcml_base_1_0;
u8 cfg_rx_reserve_7_0;
u8 cfg_rx_reserve_15_8;
u8 cfg_rxterm_2_0;
u8 cfg_fom_selm;
u8 cfg_rx_sp_ctle_1_0;
u8 cfg_isel_ctle_1_0;
u8 cfg_vga_ctrl_byp_4_0;
u8 cfg_vga_byp;
u8 cfg_agc_adpt_byp;
u8 cfg_eqr_byp;
u8 cfg_eqr_force_3_0;
u8 cfg_eqc_force_3_0;
u8 cfg_sum_setcm_en;
u8 cfg_init_pos_iscan_6_0;
u8 cfg_init_pos_ipi_6_0;
u8 cfg_dfedig_m_2_0;
u8 cfg_en_dfedig;
u8 cfg_pi_DFE_en;
u8 cfg_tx2rx_lp_en;
u8 cfg_txlb_en;
u8 cfg_rx2tx_lp_en;
u8 cfg_rxlb_en;
u8 r_tx_pol_inv;
u8 r_rx_pol_inv;
};
struct sparx5_sd10g28_media_preset {
u8 cfg_en_adv;
u8 cfg_en_main;
u8 cfg_en_dly;
u8 cfg_tap_adv_3_0;
u8 cfg_tap_main;
u8 cfg_tap_dly_4_0;
u8 cfg_vga_ctrl_3_0;
u8 cfg_vga_cp_2_0;
u8 cfg_eq_res_3_0;
u8 cfg_eq_r_byp;
u8 cfg_eq_c_force_3_0;
u8 cfg_alos_thr_3_0;
};
struct sparx5_sd10g28_mode_preset {
u8 bwidth; /* interface width: 10/16/20/32/64 */
enum sparx5_10g28cmu_mode cmu_sel; /* Device/Mode serdes uses */
u8 rate; /* Rate of network interface */
u8 dfe_tap;
u8 dfe_enable;
u8 pi_bw_gen1;
u8 duty_cycle; /* Set output level to half/full */
};
struct sparx5_sd10g28_args {
bool skip_cmu_cfg:1; /* Enable/disable CMU cfg */
bool no_pwrcycle:1; /* Omit initial power-cycle */
bool txinvert:1; /* Enable inversion of output data */
bool rxinvert:1; /* Enable inversion of input data */
bool txmargin:1; /* Set output level to half/full */
u16 txswing; /* Set output level */
bool mute:1; /* Mute Output Buffer */
bool is_6g:1;
bool reg_rst:1;
};
struct sparx5_sd10g28_params {
u8 cmu_sel;
u8 is_6g;
u8 skip_cmu_cfg;
u8 cfg_lane_reserve_7_0;
u8 cfg_ssc_rtl_clk_sel;
u8 cfg_lane_reserve_15_8;
u8 cfg_txrate_1_0;
u8 cfg_rxrate_1_0;
u8 r_d_width_ctrl_2_0;
u8 cfg_pma_tx_ck_bitwidth_2_0;
u8 cfg_rxdiv_sel_2_0;
u8 r_pcs2pma_phymode_4_0;
u8 cfg_lane_id_2_0;
u8 cfg_cdrck_en;
u8 cfg_dfeck_en;
u8 cfg_dfe_pd;
u8 cfg_dfetap_en_5_1;
u8 cfg_erramp_pd;
u8 cfg_pi_DFE_en;
u8 cfg_pi_en;
u8 cfg_pd_ctle;
u8 cfg_summer_en;
u8 cfg_pd_rx_cktree;
u8 cfg_pd_clk;
u8 cfg_pd_cml;
u8 cfg_pd_driver;
u8 cfg_rx_reg_pu;
u8 cfg_d_cdr_pd;
u8 cfg_pd_sq;
u8 cfg_rxdet_en;
u8 cfg_rxdet_str;
u8 r_multi_lane_mode;
u8 cfg_en_adv;
u8 cfg_en_main;
u8 cfg_en_dly;
u8 cfg_tap_adv_3_0;
u8 cfg_tap_main;
u8 cfg_tap_dly_4_0;
u8 cfg_vga_ctrl_3_0;
u8 cfg_vga_cp_2_0;
u8 cfg_eq_res_3_0;
u8 cfg_eq_r_byp;
u8 cfg_eq_c_force_3_0;
u8 cfg_en_dfedig;
u8 cfg_sum_setcm_en;
u8 cfg_en_preemph;
u8 cfg_itx_ippreemp_base_1_0;
u8 cfg_itx_ipdriver_base_2_0;
u8 cfg_ibias_tune_reserve_5_0;
u8 cfg_txswing_half;
u8 cfg_dis_2nd_order;
u8 cfg_rx_ssc_lh;
u8 cfg_pi_floop_steps_1_0;
u8 cfg_pi_ext_dac_23_16;
u8 cfg_pi_ext_dac_15_8;
u8 cfg_iscan_ext_dac_7_0;
u8 cfg_cdr_kf_gen1_2_0;
u8 cfg_cdr_kf_gen2_2_0;
u8 cfg_cdr_kf_gen3_2_0;
u8 cfg_cdr_kf_gen4_2_0;
u8 r_cdr_m_gen1_7_0;
u8 cfg_pi_bw_gen1_3_0;
u8 cfg_pi_bw_gen2;
u8 cfg_pi_bw_gen3;
u8 cfg_pi_bw_gen4;
u8 cfg_pi_ext_dac_7_0;
u8 cfg_pi_steps;
u8 cfg_mp_max_3_0;
u8 cfg_rstn_dfedig;
u8 cfg_alos_thr_3_0;
u8 cfg_predrv_slewrate_1_0;
u8 cfg_itx_ipcml_base_1_0;
u8 cfg_ip_pre_base_1_0;
u8 r_cdr_m_gen2_7_0;
u8 r_cdr_m_gen3_7_0;
u8 r_cdr_m_gen4_7_0;
u8 r_en_auto_cdr_rstn;
u8 cfg_oscal_afe;
u8 cfg_pd_osdac_afe;
u8 cfg_resetb_oscal_afe[2];
u8 cfg_center_spreading;
u8 cfg_m_cnt_maxval_4_0;
u8 cfg_ncnt_maxval_7_0;
u8 cfg_ncnt_maxval_10_8;
u8 cfg_ssc_en;
u8 cfg_tx2rx_lp_en;
u8 cfg_txlb_en;
u8 cfg_rx2tx_lp_en;
u8 cfg_rxlb_en;
u8 r_tx_pol_inv;
u8 r_rx_pol_inv;
u8 fx_100;
};
static struct sparx5_sd25g28_media_preset media_presets_25g[] = {
{ /* ETH_MEDIA_DEFAULT */
.cfg_en_adv = 0,
.cfg_en_main = 1,
.cfg_en_dly = 0,
.cfg_tap_adv_3_0 = 0,
.cfg_tap_main = 1,
.cfg_tap_dly_4_0 = 0,
.cfg_eq_c_force_3_0 = 0xf,
.cfg_vga_ctrl_byp_4_0 = 4,
.cfg_eq_r_force_3_0 = 12,
.cfg_alos_thr_2_0 = 7,
},
{ /* ETH_MEDIA_SR */
.cfg_en_adv = 1,
.cfg_en_main = 1,
.cfg_en_dly = 1,
.cfg_tap_adv_3_0 = 0,
.cfg_tap_main = 1,
.cfg_tap_dly_4_0 = 0x10,
.cfg_eq_c_force_3_0 = 0xf,
.cfg_vga_ctrl_byp_4_0 = 8,
.cfg_eq_r_force_3_0 = 4,
.cfg_alos_thr_2_0 = 0,
},
{ /* ETH_MEDIA_DAC */
.cfg_en_adv = 0,
.cfg_en_main = 1,
.cfg_en_dly = 0,
.cfg_tap_adv_3_0 = 0,
.cfg_tap_main = 1,
.cfg_tap_dly_4_0 = 0,
.cfg_eq_c_force_3_0 = 0xf,
.cfg_vga_ctrl_byp_4_0 = 8,
.cfg_eq_r_force_3_0 = 0xc,
.cfg_alos_thr_2_0 = 0,
},
};
static struct sparx5_sd25g28_mode_preset mode_presets_25g[] = {
{ /* SPX5_SD25G28_MODE_PRESET_25000 */
.bitwidth = 40,
.tx_pre_div = 0,
.fifo_ck_div = 0,
.pre_divsel = 1,
.vco_div_mode = 0,
.sel_div = 15,
.ck_bitwidth = 3,
.subrate = 0,
.com_txcal_en = 0,
.com_tx_reserve_msb = (0x26 << 1),
.com_tx_reserve_lsb = 0xf0,
.cfg_itx_ipcml_base = 0,
.tx_reserve_msb = 0xcc,
.tx_reserve_lsb = 0xfe,
.bw = 3,
.rxterm = 0,
.dfe_enable = 1,
.dfe_tap = 0x1f,
.txmargin = 1,
.cfg_ctle_rstn = 1,
.r_dfe_rstn = 1,
.cfg_pi_bw_3_0 = 0,
.tx_tap_dly = 8,
.tx_tap_adv = 0xc,
},
{ /* SPX5_SD25G28_MODE_PRESET_10000 */
.bitwidth = 64,
.tx_pre_div = 0,
.fifo_ck_div = 2,
.pre_divsel = 0,
.vco_div_mode = 1,
.sel_div = 9,
.ck_bitwidth = 0,
.subrate = 0,
.com_txcal_en = 1,
.com_tx_reserve_msb = (0x20 << 1),
.com_tx_reserve_lsb = 0x40,
.cfg_itx_ipcml_base = 0,
.tx_reserve_msb = 0x4c,
.tx_reserve_lsb = 0x44,
.bw = 3,
.cfg_pi_bw_3_0 = 0,
.rxterm = 3,
.dfe_enable = 1,
.dfe_tap = 0x1f,
.txmargin = 0,
.cfg_ctle_rstn = 1,
.r_dfe_rstn = 1,
.tx_tap_dly = 0,
.tx_tap_adv = 0,
},
{ /* SPX5_SD25G28_MODE_PRESET_5000 */
.bitwidth = 64,
.tx_pre_div = 0,
.fifo_ck_div = 2,
.pre_divsel = 0,
.vco_div_mode = 2,
.sel_div = 9,
.ck_bitwidth = 0,
.subrate = 0,
.com_txcal_en = 1,
.com_tx_reserve_msb = (0x20 << 1),
.com_tx_reserve_lsb = 0,
.cfg_itx_ipcml_base = 0,
.tx_reserve_msb = 0xe,
.tx_reserve_lsb = 0x80,
.bw = 0,
.rxterm = 0,
.cfg_pi_bw_3_0 = 6,
.dfe_enable = 0,
.dfe_tap = 0,
.tx_tap_dly = 0,
.tx_tap_adv = 0,
},
{ /* SPX5_SD25G28_MODE_PRESET_SD_2G5 */
.bitwidth = 10,
.tx_pre_div = 0,
.fifo_ck_div = 0,
.pre_divsel = 0,
.vco_div_mode = 1,
.sel_div = 6,
.ck_bitwidth = 3,
.subrate = 2,
.com_txcal_en = 1,
.com_tx_reserve_msb = (0x26 << 1),
.com_tx_reserve_lsb = (0xf << 4),
.cfg_itx_ipcml_base = 2,
.tx_reserve_msb = 0x8,
.tx_reserve_lsb = 0x8a,
.bw = 0,
.cfg_pi_bw_3_0 = 0,
.rxterm = (1 << 2),
.dfe_enable = 0,
.dfe_tap = 0,
.tx_tap_dly = 0,
.tx_tap_adv = 0,
},
{ /* SPX5_SD25G28_MODE_PRESET_1000BASEX */
.bitwidth = 10,
.tx_pre_div = 0,
.fifo_ck_div = 1,
.pre_divsel = 0,
.vco_div_mode = 1,
.sel_div = 8,
.ck_bitwidth = 3,
.subrate = 3,
.com_txcal_en = 1,
.com_tx_reserve_msb = (0x26 << 1),
.com_tx_reserve_lsb = 0xf0,
.cfg_itx_ipcml_base = 0,
.tx_reserve_msb = 0x8,
.tx_reserve_lsb = 0xce,
.bw = 0,
.rxterm = 0,
.cfg_pi_bw_3_0 = 0,
.dfe_enable = 0,
.dfe_tap = 0,
.tx_tap_dly = 0,
.tx_tap_adv = 0,
},
};
static struct sparx5_sd10g28_media_preset media_presets_10g[] = {
{ /* ETH_MEDIA_DEFAULT */
.cfg_en_adv = 0,
.cfg_en_main = 1,
.cfg_en_dly = 0,
.cfg_tap_adv_3_0 = 0,
.cfg_tap_main = 1,
.cfg_tap_dly_4_0 = 0,
.cfg_vga_ctrl_3_0 = 5,
.cfg_vga_cp_2_0 = 0,
.cfg_eq_res_3_0 = 0xa,
.cfg_eq_r_byp = 1,
.cfg_eq_c_force_3_0 = 0x8,
.cfg_alos_thr_3_0 = 0x3,
},
{ /* ETH_MEDIA_SR */
.cfg_en_adv = 1,
.cfg_en_main = 1,
.cfg_en_dly = 1,
.cfg_tap_adv_3_0 = 0,
.cfg_tap_main = 1,
.cfg_tap_dly_4_0 = 0xc,
.cfg_vga_ctrl_3_0 = 0xa,
.cfg_vga_cp_2_0 = 0x4,
.cfg_eq_res_3_0 = 0xa,
.cfg_eq_r_byp = 1,
.cfg_eq_c_force_3_0 = 0xF,
.cfg_alos_thr_3_0 = 0x3,
},
{ /* ETH_MEDIA_DAC */
.cfg_en_adv = 1,
.cfg_en_main = 1,
.cfg_en_dly = 1,
.cfg_tap_adv_3_0 = 12,
.cfg_tap_main = 1,
.cfg_tap_dly_4_0 = 8,
.cfg_vga_ctrl_3_0 = 0xa,
.cfg_vga_cp_2_0 = 4,
.cfg_eq_res_3_0 = 0xa,
.cfg_eq_r_byp = 1,
.cfg_eq_c_force_3_0 = 0xf,
.cfg_alos_thr_3_0 = 0x0,
}
};
static struct sparx5_sd10g28_mode_preset mode_presets_10g[] = {
{ /* SPX5_SD10G28_MODE_PRESET_10000 */
.bwidth = 64,
.cmu_sel = SPX5_SD10G28_CMU_MAIN,
.rate = 0x0,
.dfe_enable = 1,
.dfe_tap = 0x1f,
.pi_bw_gen1 = 0x0,
.duty_cycle = 0x2,
},
{ /* SPX5_SD10G28_MODE_PRESET_SFI_5000_6G */
.bwidth = 16,
.cmu_sel = SPX5_SD10G28_CMU_MAIN,
.rate = 0x1,
.dfe_enable = 0,
.dfe_tap = 0,
.pi_bw_gen1 = 0x5,
.duty_cycle = 0x0,
},
{ /* SPX5_SD10G28_MODE_PRESET_SFI_5000_10G */
.bwidth = 64,
.cmu_sel = SPX5_SD10G28_CMU_MAIN,
.rate = 0x1,
.dfe_enable = 0,
.dfe_tap = 0,
.pi_bw_gen1 = 0x5,
.duty_cycle = 0x0,
},
{ /* SPX5_SD10G28_MODE_PRESET_QSGMII */
.bwidth = 20,
.cmu_sel = SPX5_SD10G28_CMU_AUX1,
.rate = 0x1,
.dfe_enable = 0,
.dfe_tap = 0,
.pi_bw_gen1 = 0x5,
.duty_cycle = 0x0,
},
{ /* SPX5_SD10G28_MODE_PRESET_SD_2G5 */
.bwidth = 10,
.cmu_sel = SPX5_SD10G28_CMU_AUX2,
.rate = 0x2,
.dfe_enable = 0,
.dfe_tap = 0,
.pi_bw_gen1 = 0x7,
.duty_cycle = 0x0,
},
{ /* SPX5_SD10G28_MODE_PRESET_1000BASEX */
.bwidth = 10,
.cmu_sel = SPX5_SD10G28_CMU_AUX1,
.rate = 0x3,
.dfe_enable = 0,
.dfe_tap = 0,
.pi_bw_gen1 = 0x7,
.duty_cycle = 0x0,
},
};
/* map from SD25G28 interface width to configuration value */
static u8 sd25g28_get_iw_setting(struct device *dev, const u8 interface_width)
{
switch (interface_width) {
case 10: return 0;
case 16: return 1;
case 32: return 3;
case 40: return 4;
case 64: return 5;
default:
dev_err(dev, "%s: Illegal value %d for interface width\n",
__func__, interface_width);
}
return 0;
}
/* map from SD10G28 interface width to configuration value */
static u8 sd10g28_get_iw_setting(struct device *dev, const u8 interface_width)
{
switch (interface_width) {
case 10: return 0;
case 16: return 1;
case 20: return 2;
case 32: return 3;
case 40: return 4;
case 64: return 7;
default:
dev_err(dev, "%s: Illegal value %d for interface width\n", __func__,
interface_width);
return 0;
}
}
static int sparx5_sd10g25_get_mode_preset(struct sparx5_serdes_macro *macro,
struct sparx5_sd25g28_mode_preset *mode)
{
switch (macro->serdesmode) {
case SPX5_SD_MODE_SFI:
if (macro->speed == SPEED_25000)
*mode = mode_presets_25g[SPX5_SD25G28_MODE_PRESET_25000];
else if (macro->speed == SPEED_10000)
*mode = mode_presets_25g[SPX5_SD25G28_MODE_PRESET_10000];
else if (macro->speed == SPEED_5000)
*mode = mode_presets_25g[SPX5_SD25G28_MODE_PRESET_5000];
break;
case SPX5_SD_MODE_2G5:
*mode = mode_presets_25g[SPX5_SD25G28_MODE_PRESET_SD_2G5];
break;
case SPX5_SD_MODE_1000BASEX:
*mode = mode_presets_25g[SPX5_SD25G28_MODE_PRESET_1000BASEX];
break;
case SPX5_SD_MODE_100FX:
/* Not supported */
return -EINVAL;
default:
*mode = mode_presets_25g[SPX5_SD25G28_MODE_PRESET_25000];
break;
}
return 0;
}
static int sparx5_sd10g28_get_mode_preset(struct sparx5_serdes_macro *macro,
struct sparx5_sd10g28_mode_preset *mode,
struct sparx5_sd10g28_args *args)
{
switch (macro->serdesmode) {
case SPX5_SD_MODE_SFI:
if (macro->speed == SPEED_10000) {
*mode = mode_presets_10g[SPX5_SD10G28_MODE_PRESET_10000];
} else if (macro->speed == SPEED_5000) {
if (args->is_6g)
*mode = mode_presets_10g[SPX5_SD10G28_MODE_PRESET_SFI_5000_6G];
else
*mode = mode_presets_10g[SPX5_SD10G28_MODE_PRESET_SFI_5000_10G];
} else {
dev_err(macro->priv->dev, "%s: Illegal speed: %02u, sidx: %02u, mode (%u)",
__func__, macro->speed, macro->sidx,
macro->serdesmode);
return -EINVAL;
}
break;
case SPX5_SD_MODE_QSGMII:
*mode = mode_presets_10g[SPX5_SD10G28_MODE_PRESET_QSGMII];
break;
case SPX5_SD_MODE_2G5:
*mode = mode_presets_10g[SPX5_SD10G28_MODE_PRESET_SD_2G5];
break;
case SPX5_SD_MODE_100FX:
case SPX5_SD_MODE_1000BASEX:
*mode = mode_presets_10g[SPX5_SD10G28_MODE_PRESET_1000BASEX];
break;
default:
*mode = mode_presets_10g[SPX5_SD10G28_MODE_PRESET_10000];
break;
}
return 0;
}
static void sparx5_sd25g28_get_params(struct sparx5_serdes_macro *macro,
struct sparx5_sd25g28_media_preset *media,
struct sparx5_sd25g28_mode_preset *mode,
struct sparx5_sd25g28_args *args,
struct sparx5_sd25g28_params *params)
{
u8 iw = sd25g28_get_iw_setting(macro->priv->dev, mode->bitwidth);
struct sparx5_sd25g28_params init = {
.r_d_width_ctrl_2_0 = iw,
.r_txfifo_ck_div_pmad_2_0 = mode->fifo_ck_div,
.r_rxfifo_ck_div_pmad_2_0 = mode->fifo_ck_div,
.cfg_vco_div_mode_1_0 = mode->vco_div_mode,
.cfg_pre_divsel_1_0 = mode->pre_divsel,
.cfg_sel_div_3_0 = mode->sel_div,
.cfg_vco_start_code_3_0 = 0,
.cfg_pma_tx_ck_bitwidth_2_0 = mode->ck_bitwidth,
.cfg_tx_prediv_1_0 = mode->tx_pre_div,
.cfg_rxdiv_sel_2_0 = mode->ck_bitwidth,
.cfg_tx_subrate_2_0 = mode->subrate,
.cfg_rx_subrate_2_0 = mode->subrate,
.r_multi_lane_mode = 0,
.cfg_cdrck_en = 1,
.cfg_dfeck_en = mode->dfe_enable,
.cfg_dfe_pd = mode->dfe_enable == 1 ? 0 : 1,
.cfg_dfedmx_pd = 1,
.cfg_dfetap_en_5_1 = mode->dfe_tap,
.cfg_dmux_pd = 0,
.cfg_dmux_clk_pd = 1,
.cfg_erramp_pd = mode->dfe_enable == 1 ? 0 : 1,
.cfg_pi_DFE_en = mode->dfe_enable,
.cfg_pi_en = 1,
.cfg_pd_ctle = 0,
.cfg_summer_en = 1,
.cfg_pmad_ck_pd = 0,
.cfg_pd_clk = 0,
.cfg_pd_cml = 0,
.cfg_pd_driver = 0,
.cfg_rx_reg_pu = 1,
.cfg_pd_rms_det = 1,
.cfg_dcdr_pd = 0,
.cfg_ecdr_pd = 1,
.cfg_pd_sq = 1,
.cfg_itx_ipdriver_base_2_0 = mode->txmargin,
.cfg_tap_dly_4_0 = media->cfg_tap_dly_4_0,
.cfg_tap_main = media->cfg_tap_main,
.cfg_en_main = media->cfg_en_main,
.cfg_tap_adv_3_0 = media->cfg_tap_adv_3_0,
.cfg_en_adv = media->cfg_en_adv,
.cfg_en_dly = media->cfg_en_dly,
.cfg_iscan_en = 0,
.l1_pcs_en_fast_iscan = 0,
.l0_cfg_bw_1_0 = 0,
.cfg_en_dummy = 0,
.cfg_pll_reserve_3_0 = args->com_pll_reserve,
.l0_cfg_txcal_en = mode->com_txcal_en,
.l0_cfg_tx_reserve_15_8 = mode->com_tx_reserve_msb,
.l0_cfg_tx_reserve_7_0 = mode->com_tx_reserve_lsb,
.cfg_tx_reserve_15_8 = mode->tx_reserve_msb,
.cfg_tx_reserve_7_0 = mode->tx_reserve_lsb,
.cfg_bw_1_0 = mode->bw,
.cfg_txcal_man_en = 1,
.cfg_phase_man_4_0 = 0,
.cfg_quad_man_1_0 = 0,
.cfg_txcal_shift_code_5_0 = 2,
.cfg_txcal_valid_sel_3_0 = 4,
.cfg_txcal_en = 0,
.cfg_cdr_kf_2_0 = 1,
.cfg_cdr_m_7_0 = 6,
.cfg_pi_bw_3_0 = mode->cfg_pi_bw_3_0,
.cfg_pi_steps_1_0 = 0,
.cfg_dis_2ndorder = 1,
.cfg_ctle_rstn = mode->cfg_ctle_rstn,
.r_dfe_rstn = mode->r_dfe_rstn,
.cfg_alos_thr_2_0 = media->cfg_alos_thr_2_0,
.cfg_itx_ipcml_base_1_0 = mode->cfg_itx_ipcml_base,
.cfg_rx_reserve_7_0 = 0xbf,
.cfg_rx_reserve_15_8 = 0x61,
.cfg_rxterm_2_0 = mode->rxterm,
.cfg_fom_selm = 0,
.cfg_rx_sp_ctle_1_0 = 0,
.cfg_isel_ctle_1_0 = 0,
.cfg_vga_ctrl_byp_4_0 = media->cfg_vga_ctrl_byp_4_0,
.cfg_vga_byp = 1,
.cfg_agc_adpt_byp = 1,
.cfg_eqr_byp = 1,
.cfg_eqr_force_3_0 = media->cfg_eq_r_force_3_0,
.cfg_eqc_force_3_0 = media->cfg_eq_c_force_3_0,
.cfg_sum_setcm_en = 1,
.cfg_pi_dfe_en = 1,
.cfg_init_pos_iscan_6_0 = 6,
.cfg_init_pos_ipi_6_0 = 9,
.cfg_dfedig_m_2_0 = 6,
.cfg_en_dfedig = mode->dfe_enable,
.r_d_width_ctrl_from_hwt = 0,
.r_reg_manual = 1,
.reg_rst = args->reg_rst,
.cfg_jc_byp = 1,
.cfg_common_reserve_7_0 = 1,
.cfg_pll_lol_set = 1,
.cfg_tx2rx_lp_en = 0,
.cfg_txlb_en = 0,
.cfg_rx2tx_lp_en = 0,
.cfg_rxlb_en = 0,
.r_tx_pol_inv = args->txinvert,
.r_rx_pol_inv = args->rxinvert,
};
*params = init;
}
static void sparx5_sd10g28_get_params(struct sparx5_serdes_macro *macro,
struct sparx5_sd10g28_media_preset *media,
struct sparx5_sd10g28_mode_preset *mode,
struct sparx5_sd10g28_args *args,
struct sparx5_sd10g28_params *params)
{
u8 iw = sd10g28_get_iw_setting(macro->priv->dev, mode->bwidth);
struct sparx5_sd10g28_params init = {
.skip_cmu_cfg = args->skip_cmu_cfg,
.is_6g = args->is_6g,
.cmu_sel = mode->cmu_sel,
.cfg_lane_reserve_7_0 = (mode->cmu_sel % 2) << 6,
.cfg_ssc_rtl_clk_sel = (mode->cmu_sel / 2),
.cfg_lane_reserve_15_8 = mode->duty_cycle,
.cfg_txrate_1_0 = mode->rate,
.cfg_rxrate_1_0 = mode->rate,
.fx_100 = macro->serdesmode == SPX5_SD_MODE_100FX,
.r_d_width_ctrl_2_0 = iw,
.cfg_pma_tx_ck_bitwidth_2_0 = iw,
.cfg_rxdiv_sel_2_0 = iw,
.r_pcs2pma_phymode_4_0 = 0,
.cfg_lane_id_2_0 = 0,
.cfg_cdrck_en = 1,
.cfg_dfeck_en = mode->dfe_enable,
.cfg_dfe_pd = (mode->dfe_enable == 1) ? 0 : 1,
.cfg_dfetap_en_5_1 = mode->dfe_tap,
.cfg_erramp_pd = (mode->dfe_enable == 1) ? 0 : 1,
.cfg_pi_DFE_en = mode->dfe_enable,
.cfg_pi_en = 1,
.cfg_pd_ctle = 0,
.cfg_summer_en = 1,
.cfg_pd_rx_cktree = 0,
.cfg_pd_clk = 0,
.cfg_pd_cml = 0,
.cfg_pd_driver = 0,
.cfg_rx_reg_pu = 1,
.cfg_d_cdr_pd = 0,
.cfg_pd_sq = mode->dfe_enable,
.cfg_rxdet_en = 0,
.cfg_rxdet_str = 0,
.r_multi_lane_mode = 0,
.cfg_en_adv = media->cfg_en_adv,
.cfg_en_main = 1,
.cfg_en_dly = media->cfg_en_dly,
.cfg_tap_adv_3_0 = media->cfg_tap_adv_3_0,
.cfg_tap_main = media->cfg_tap_main,
.cfg_tap_dly_4_0 = media->cfg_tap_dly_4_0,
.cfg_vga_ctrl_3_0 = media->cfg_vga_ctrl_3_0,
.cfg_vga_cp_2_0 = media->cfg_vga_cp_2_0,
.cfg_eq_res_3_0 = media->cfg_eq_res_3_0,
.cfg_eq_r_byp = media->cfg_eq_r_byp,
.cfg_eq_c_force_3_0 = media->cfg_eq_c_force_3_0,
.cfg_en_dfedig = mode->dfe_enable,
.cfg_sum_setcm_en = 1,
.cfg_en_preemph = 0,
.cfg_itx_ippreemp_base_1_0 = 0,
.cfg_itx_ipdriver_base_2_0 = (args->txswing >> 6),
.cfg_ibias_tune_reserve_5_0 = (args->txswing & 63),
.cfg_txswing_half = (args->txmargin),
.cfg_dis_2nd_order = 0x1,
.cfg_rx_ssc_lh = 0x0,
.cfg_pi_floop_steps_1_0 = 0x0,
.cfg_pi_ext_dac_23_16 = (1 << 5),
.cfg_pi_ext_dac_15_8 = (0 << 6),
.cfg_iscan_ext_dac_7_0 = (1 << 7) + 9,
.cfg_cdr_kf_gen1_2_0 = 1,
.cfg_cdr_kf_gen2_2_0 = 1,
.cfg_cdr_kf_gen3_2_0 = 1,
.cfg_cdr_kf_gen4_2_0 = 1,
.r_cdr_m_gen1_7_0 = 4,
.cfg_pi_bw_gen1_3_0 = mode->pi_bw_gen1,
.cfg_pi_bw_gen2 = mode->pi_bw_gen1,
.cfg_pi_bw_gen3 = mode->pi_bw_gen1,
.cfg_pi_bw_gen4 = mode->pi_bw_gen1,
.cfg_pi_ext_dac_7_0 = 3,
.cfg_pi_steps = 0,
.cfg_mp_max_3_0 = 1,
.cfg_rstn_dfedig = mode->dfe_enable,
.cfg_alos_thr_3_0 = media->cfg_alos_thr_3_0,
.cfg_predrv_slewrate_1_0 = 3,
.cfg_itx_ipcml_base_1_0 = 0,
.cfg_ip_pre_base_1_0 = 0,
.r_cdr_m_gen2_7_0 = 2,
.r_cdr_m_gen3_7_0 = 2,
.r_cdr_m_gen4_7_0 = 2,
.r_en_auto_cdr_rstn = 0,
.cfg_oscal_afe = 1,
.cfg_pd_osdac_afe = 0,
.cfg_resetb_oscal_afe[0] = 0,
.cfg_resetb_oscal_afe[1] = 1,
.cfg_center_spreading = 0,
.cfg_m_cnt_maxval_4_0 = 15,
.cfg_ncnt_maxval_7_0 = 32,
.cfg_ncnt_maxval_10_8 = 6,
.cfg_ssc_en = 1,
.cfg_tx2rx_lp_en = 0,
.cfg_txlb_en = 0,
.cfg_rx2tx_lp_en = 0,
.cfg_rxlb_en = 0,
.r_tx_pol_inv = args->txinvert,
.r_rx_pol_inv = args->rxinvert,
};
*params = init;
}
static int sparx5_cmu_apply_cfg(struct sparx5_serdes_private *priv,
u32 cmu_idx,
void __iomem *cmu_tgt,
void __iomem *cmu_cfg_tgt,
u32 spd10g)
{
void __iomem **regs = priv->regs;
struct device *dev = priv->dev;
int value;
cmu_tgt = sdx5_inst_get(priv, TARGET_SD_CMU, cmu_idx);
cmu_cfg_tgt = sdx5_inst_get(priv, TARGET_SD_CMU_CFG, cmu_idx);
if (cmu_idx == 1 || cmu_idx == 4 || cmu_idx == 7 ||
cmu_idx == 10 || cmu_idx == 13) {
spd10g = 0;
}
sdx5_inst_rmw(SD_CMU_CFG_SD_CMU_CFG_EXT_CFG_RST_SET(1),
SD_CMU_CFG_SD_CMU_CFG_EXT_CFG_RST,
cmu_cfg_tgt,
SD_CMU_CFG_SD_CMU_CFG(cmu_idx));
sdx5_inst_rmw(SD_CMU_CFG_SD_CMU_CFG_EXT_CFG_RST_SET(0),
SD_CMU_CFG_SD_CMU_CFG_EXT_CFG_RST,
cmu_cfg_tgt,
SD_CMU_CFG_SD_CMU_CFG(cmu_idx));
sdx5_inst_rmw(SD_CMU_CFG_SD_CMU_CFG_CMU_RST_SET(1),
SD_CMU_CFG_SD_CMU_CFG_CMU_RST,
cmu_cfg_tgt,
SD_CMU_CFG_SD_CMU_CFG(cmu_idx));
sdx5_inst_rmw(SD_CMU_CMU_45_R_DWIDTHCTRL_FROM_HWT_SET(0x1) |
SD_CMU_CMU_45_R_REFCK_SSC_EN_FROM_HWT_SET(0x1) |
SD_CMU_CMU_45_R_LINK_BUF_EN_FROM_HWT_SET(0x1) |
SD_CMU_CMU_45_R_BIAS_EN_FROM_HWT_SET(0x1) |
SD_CMU_CMU_45_R_EN_RATECHG_CTRL_SET(0x0),
SD_CMU_CMU_45_R_DWIDTHCTRL_FROM_HWT |
SD_CMU_CMU_45_R_REFCK_SSC_EN_FROM_HWT |
SD_CMU_CMU_45_R_LINK_BUF_EN_FROM_HWT |
SD_CMU_CMU_45_R_BIAS_EN_FROM_HWT |
SD_CMU_CMU_45_R_EN_RATECHG_CTRL,
cmu_tgt,
SD_CMU_CMU_45(cmu_idx));
sdx5_inst_rmw(SD_CMU_CMU_47_R_PCS2PMA_PHYMODE_4_0_SET(0),
SD_CMU_CMU_47_R_PCS2PMA_PHYMODE_4_0,
cmu_tgt,
SD_CMU_CMU_47(cmu_idx));
sdx5_inst_rmw(SD_CMU_CMU_1B_CFG_RESERVE_7_0_SET(0),
SD_CMU_CMU_1B_CFG_RESERVE_7_0,
cmu_tgt,
SD_CMU_CMU_1B(cmu_idx));
sdx5_inst_rmw(SD_CMU_CMU_0D_CFG_JC_BYP_SET(0x1),
SD_CMU_CMU_0D_CFG_JC_BYP,
cmu_tgt,
SD_CMU_CMU_0D(cmu_idx));
sdx5_inst_rmw(SD_CMU_CMU_1F_CFG_VTUNE_SEL_SET(1),
SD_CMU_CMU_1F_CFG_VTUNE_SEL,
cmu_tgt,
SD_CMU_CMU_1F(cmu_idx));
sdx5_inst_rmw(SD_CMU_CMU_00_CFG_PLL_TP_SEL_1_0_SET(3),
SD_CMU_CMU_00_CFG_PLL_TP_SEL_1_0,
cmu_tgt,
SD_CMU_CMU_00(cmu_idx));