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ohci1394.c
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ohci1394.c
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/*
* ohci1394.c - driver for OHCI 1394 boards
* Copyright (C)1999,2000 Sebastien Rougeaux <[email protected]>
* Gord Peters <[email protected]>
* 2001 Ben Collins <[email protected]>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software Foundation,
* Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
/*
* Things known to be working:
* . Async Request Transmit
* . Async Response Receive
* . Async Request Receive
* . Async Response Transmit
* . Iso Receive
* . DMA mmap for iso receive
* . Config ROM generation
*
* Things implemented, but still in test phase:
* . Iso Transmit
* . Async Stream Packets Transmit (Receive done via Iso interface)
*
* Things not implemented:
* . DMA error recovery
*
* Known bugs:
* . devctl BUS_RESET arg confusion (reset type or root holdoff?)
* added LONG_RESET_ROOT and SHORT_RESET_ROOT for root holdoff --kk
*/
/*
* Acknowledgments:
*
* Adam J Richter <[email protected]>
* . Use of pci_class to find device
*
* Emilie Chung <[email protected]>
* . Tip on Async Request Filter
*
* Pascal Drolet <[email protected]>
* . Various tips for optimization and functionnalities
*
* Robert Ficklin <[email protected]>
* . Loop in irq_handler
*
* James Goodwin <[email protected]>
* . Various tips on initialization, self-id reception, etc.
*
* Albrecht Dress <[email protected]>
* . Apple PowerBook detection
*
* Daniel Kobras <[email protected]>
* . Reset the board properly before leaving + misc cleanups
*
* Leon van Stuivenberg <[email protected]>
* . Bug fixes
*
* Ben Collins <[email protected]>
* . Working big-endian support
* . Updated to 2.4.x module scheme (PCI aswell)
* . Config ROM generation
*
* Manfred Weihs <[email protected]>
* . Reworked code for initiating bus resets
* (long, short, with or without hold-off)
*
* Nandu Santhi <[email protected]>
* . Added support for nVidia nForce2 onboard Firewire chipset
*
*/
#include <linux/bitops.h>
#include <linux/kernel.h>
#include <linux/list.h>
#include <linux/slab.h>
#include <linux/interrupt.h>
#include <linux/wait.h>
#include <linux/errno.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/pci.h>
#include <linux/fs.h>
#include <linux/poll.h>
#include <asm/byteorder.h>
#include <asm/atomic.h>
#include <asm/uaccess.h>
#include <linux/delay.h>
#include <linux/spinlock.h>
#include <asm/pgtable.h>
#include <asm/page.h>
#include <asm/irq.h>
#include <linux/types.h>
#include <linux/vmalloc.h>
#include <linux/init.h>
#ifdef CONFIG_PPC_PMAC
#include <asm/machdep.h>
#include <asm/pmac_feature.h>
#include <asm/prom.h>
#include <asm/pci-bridge.h>
#endif
#include "csr1212.h"
#include "ieee1394.h"
#include "ieee1394_types.h"
#include "hosts.h"
#include "dma.h"
#include "iso.h"
#include "ieee1394_core.h"
#include "highlevel.h"
#include "ohci1394.h"
#ifdef CONFIG_IEEE1394_VERBOSEDEBUG
#define OHCI1394_DEBUG
#endif
#ifdef DBGMSG
#undef DBGMSG
#endif
#ifdef OHCI1394_DEBUG
#define DBGMSG(fmt, args...) \
printk(KERN_INFO "%s: fw-host%d: " fmt "\n" , OHCI1394_DRIVER_NAME, ohci->host->id , ## args)
#else
#define DBGMSG(fmt, args...) do {} while (0)
#endif
/* print general (card independent) information */
#define PRINT_G(level, fmt, args...) \
printk(level "%s: " fmt "\n" , OHCI1394_DRIVER_NAME , ## args)
/* print card specific information */
#define PRINT(level, fmt, args...) \
printk(level "%s: fw-host%d: " fmt "\n" , OHCI1394_DRIVER_NAME, ohci->host->id , ## args)
/* Module Parameters */
static int phys_dma = 1;
module_param(phys_dma, int, 0444);
MODULE_PARM_DESC(phys_dma, "Enable physical DMA (default = 1).");
static void dma_trm_tasklet(unsigned long data);
static void dma_trm_reset(struct dma_trm_ctx *d);
static int alloc_dma_rcv_ctx(struct ti_ohci *ohci, struct dma_rcv_ctx *d,
enum context_type type, int ctx, int num_desc,
int buf_size, int split_buf_size, int context_base);
static void free_dma_rcv_ctx(struct dma_rcv_ctx *d);
static int alloc_dma_trm_ctx(struct ti_ohci *ohci, struct dma_trm_ctx *d,
enum context_type type, int ctx, int num_desc,
int context_base);
static void ohci1394_pci_remove(struct pci_dev *pdev);
#ifndef __LITTLE_ENDIAN
static const size_t hdr_sizes[] = {
3, /* TCODE_WRITEQ */
4, /* TCODE_WRITEB */
3, /* TCODE_WRITE_RESPONSE */
0, /* reserved */
3, /* TCODE_READQ */
4, /* TCODE_READB */
3, /* TCODE_READQ_RESPONSE */
4, /* TCODE_READB_RESPONSE */
1, /* TCODE_CYCLE_START */
4, /* TCODE_LOCK_REQUEST */
2, /* TCODE_ISO_DATA */
4, /* TCODE_LOCK_RESPONSE */
/* rest is reserved or link-internal */
};
static inline void header_le32_to_cpu(quadlet_t *data, unsigned char tcode)
{
size_t size;
if (unlikely(tcode >= ARRAY_SIZE(hdr_sizes)))
return;
size = hdr_sizes[tcode];
while (size--)
data[size] = le32_to_cpu(data[size]);
}
#else
#define header_le32_to_cpu(w,x) do {} while (0)
#endif /* !LITTLE_ENDIAN */
/***********************************
* IEEE-1394 functionality section *
***********************************/
static u8 get_phy_reg(struct ti_ohci *ohci, u8 addr)
{
int i;
unsigned long flags;
quadlet_t r;
spin_lock_irqsave (&ohci->phy_reg_lock, flags);
reg_write(ohci, OHCI1394_PhyControl, (addr << 8) | 0x00008000);
for (i = 0; i < OHCI_LOOP_COUNT; i++) {
if (reg_read(ohci, OHCI1394_PhyControl) & 0x80000000)
break;
mdelay(1);
}
r = reg_read(ohci, OHCI1394_PhyControl);
if (i >= OHCI_LOOP_COUNT)
PRINT (KERN_ERR, "Get PHY Reg timeout [0x%08x/0x%08x/%d]",
r, r & 0x80000000, i);
spin_unlock_irqrestore (&ohci->phy_reg_lock, flags);
return (r & 0x00ff0000) >> 16;
}
static void set_phy_reg(struct ti_ohci *ohci, u8 addr, u8 data)
{
int i;
unsigned long flags;
u32 r = 0;
spin_lock_irqsave (&ohci->phy_reg_lock, flags);
reg_write(ohci, OHCI1394_PhyControl, (addr << 8) | data | 0x00004000);
for (i = 0; i < OHCI_LOOP_COUNT; i++) {
r = reg_read(ohci, OHCI1394_PhyControl);
if (!(r & 0x00004000))
break;
mdelay(1);
}
if (i == OHCI_LOOP_COUNT)
PRINT (KERN_ERR, "Set PHY Reg timeout [0x%08x/0x%08x/%d]",
r, r & 0x00004000, i);
spin_unlock_irqrestore (&ohci->phy_reg_lock, flags);
return;
}
/* Or's our value into the current value */
static void set_phy_reg_mask(struct ti_ohci *ohci, u8 addr, u8 data)
{
u8 old;
old = get_phy_reg (ohci, addr);
old |= data;
set_phy_reg (ohci, addr, old);
return;
}
static void handle_selfid(struct ti_ohci *ohci, struct hpsb_host *host,
int phyid, int isroot)
{
quadlet_t *q = ohci->selfid_buf_cpu;
quadlet_t self_id_count=reg_read(ohci, OHCI1394_SelfIDCount);
size_t size;
quadlet_t q0, q1;
/* Check status of self-id reception */
if (ohci->selfid_swap)
q0 = le32_to_cpu(q[0]);
else
q0 = q[0];
if ((self_id_count & 0x80000000) ||
((self_id_count & 0x00FF0000) != (q0 & 0x00FF0000))) {
PRINT(KERN_ERR,
"Error in reception of SelfID packets [0x%08x/0x%08x] (count: %d)",
self_id_count, q0, ohci->self_id_errors);
/* Tip by James Goodwin <[email protected]>:
* We had an error, generate another bus reset in response. */
if (ohci->self_id_errors<OHCI1394_MAX_SELF_ID_ERRORS) {
set_phy_reg_mask (ohci, 1, 0x40);
ohci->self_id_errors++;
} else {
PRINT(KERN_ERR,
"Too many errors on SelfID error reception, giving up!");
}
return;
}
/* SelfID Ok, reset error counter. */
ohci->self_id_errors = 0;
size = ((self_id_count & 0x00001FFC) >> 2) - 1;
q++;
while (size > 0) {
if (ohci->selfid_swap) {
q0 = le32_to_cpu(q[0]);
q1 = le32_to_cpu(q[1]);
} else {
q0 = q[0];
q1 = q[1];
}
if (q0 == ~q1) {
DBGMSG ("SelfID packet 0x%x received", q0);
hpsb_selfid_received(host, cpu_to_be32(q0));
if (((q0 & 0x3f000000) >> 24) == phyid)
DBGMSG ("SelfID for this node is 0x%08x", q0);
} else {
PRINT(KERN_ERR,
"SelfID is inconsistent [0x%08x/0x%08x]", q0, q1);
}
q += 2;
size -= 2;
}
DBGMSG("SelfID complete");
return;
}
static void ohci_soft_reset(struct ti_ohci *ohci) {
int i;
reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset);
for (i = 0; i < OHCI_LOOP_COUNT; i++) {
if (!(reg_read(ohci, OHCI1394_HCControlSet) & OHCI1394_HCControl_softReset))
break;
mdelay(1);
}
DBGMSG ("Soft reset finished");
}
/* Generate the dma receive prgs and start the context */
static void initialize_dma_rcv_ctx(struct dma_rcv_ctx *d, int generate_irq)
{
struct ti_ohci *ohci = (struct ti_ohci*)(d->ohci);
int i;
ohci1394_stop_context(ohci, d->ctrlClear, NULL);
for (i=0; i<d->num_desc; i++) {
u32 c;
c = DMA_CTL_INPUT_MORE | DMA_CTL_UPDATE | DMA_CTL_BRANCH;
if (generate_irq)
c |= DMA_CTL_IRQ;
d->prg_cpu[i]->control = cpu_to_le32(c | d->buf_size);
/* End of descriptor list? */
if (i + 1 < d->num_desc) {
d->prg_cpu[i]->branchAddress =
cpu_to_le32((d->prg_bus[i+1] & 0xfffffff0) | 0x1);
} else {
d->prg_cpu[i]->branchAddress =
cpu_to_le32((d->prg_bus[0] & 0xfffffff0));
}
d->prg_cpu[i]->address = cpu_to_le32(d->buf_bus[i]);
d->prg_cpu[i]->status = cpu_to_le32(d->buf_size);
}
d->buf_ind = 0;
d->buf_offset = 0;
if (d->type == DMA_CTX_ISO) {
/* Clear contextControl */
reg_write(ohci, d->ctrlClear, 0xffffffff);
/* Set bufferFill, isochHeader, multichannel for IR context */
reg_write(ohci, d->ctrlSet, 0xd0000000);
/* Set the context match register to match on all tags */
reg_write(ohci, d->ctxtMatch, 0xf0000000);
/* Clear the multi channel mask high and low registers */
reg_write(ohci, OHCI1394_IRMultiChanMaskHiClear, 0xffffffff);
reg_write(ohci, OHCI1394_IRMultiChanMaskLoClear, 0xffffffff);
/* Set up isoRecvIntMask to generate interrupts */
reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << d->ctx);
}
/* Tell the controller where the first AR program is */
reg_write(ohci, d->cmdPtr, d->prg_bus[0] | 0x1);
/* Run context */
reg_write(ohci, d->ctrlSet, 0x00008000);
DBGMSG("Receive DMA ctx=%d initialized", d->ctx);
}
/* Initialize the dma transmit context */
static void initialize_dma_trm_ctx(struct dma_trm_ctx *d)
{
struct ti_ohci *ohci = (struct ti_ohci*)(d->ohci);
/* Stop the context */
ohci1394_stop_context(ohci, d->ctrlClear, NULL);
d->prg_ind = 0;
d->sent_ind = 0;
d->free_prgs = d->num_desc;
d->branchAddrPtr = NULL;
INIT_LIST_HEAD(&d->fifo_list);
INIT_LIST_HEAD(&d->pending_list);
if (d->type == DMA_CTX_ISO) {
/* enable interrupts */
reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << d->ctx);
}
DBGMSG("Transmit DMA ctx=%d initialized", d->ctx);
}
/* Count the number of available iso contexts */
static int get_nb_iso_ctx(struct ti_ohci *ohci, int reg)
{
u32 tmp;
reg_write(ohci, reg, 0xffffffff);
tmp = reg_read(ohci, reg);
DBGMSG("Iso contexts reg: %08x implemented: %08x", reg, tmp);
/* Count the number of contexts */
return hweight32(tmp);
}
/* Global initialization */
static void ohci_initialize(struct ti_ohci *ohci)
{
quadlet_t buf;
int num_ports, i;
spin_lock_init(&ohci->phy_reg_lock);
/* Put some defaults to these undefined bus options */
buf = reg_read(ohci, OHCI1394_BusOptions);
buf |= 0x60000000; /* Enable CMC and ISC */
if (hpsb_disable_irm)
buf &= ~0x80000000;
else
buf |= 0x80000000; /* Enable IRMC */
buf &= ~0x00ff0000; /* XXX: Set cyc_clk_acc to zero for now */
buf &= ~0x18000000; /* Disable PMC and BMC */
reg_write(ohci, OHCI1394_BusOptions, buf);
/* Set the bus number */
reg_write(ohci, OHCI1394_NodeID, 0x0000ffc0);
/* Enable posted writes */
reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_postedWriteEnable);
/* Clear link control register */
reg_write(ohci, OHCI1394_LinkControlClear, 0xffffffff);
/* Enable cycle timer and cycle master and set the IRM
* contender bit in our self ID packets if appropriate. */
reg_write(ohci, OHCI1394_LinkControlSet,
OHCI1394_LinkControl_CycleTimerEnable |
OHCI1394_LinkControl_CycleMaster);
i = get_phy_reg(ohci, 4) | PHY_04_LCTRL;
if (hpsb_disable_irm)
i &= ~PHY_04_CONTENDER;
else
i |= PHY_04_CONTENDER;
set_phy_reg(ohci, 4, i);
/* Set up self-id dma buffer */
reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->selfid_buf_bus);
/* enable self-id */
reg_write(ohci, OHCI1394_LinkControlSet, OHCI1394_LinkControl_RcvSelfID);
/* Set the Config ROM mapping register */
reg_write(ohci, OHCI1394_ConfigROMmap, ohci->csr_config_rom_bus);
/* Now get our max packet size */
ohci->max_packet_size =
1<<(((reg_read(ohci, OHCI1394_BusOptions)>>12)&0xf)+1);
/* Clear the interrupt mask */
reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 0xffffffff);
reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 0xffffffff);
/* Clear the interrupt mask */
reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 0xffffffff);
reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 0xffffffff);
/* Initialize AR dma */
initialize_dma_rcv_ctx(&ohci->ar_req_context, 0);
initialize_dma_rcv_ctx(&ohci->ar_resp_context, 0);
/* Initialize AT dma */
initialize_dma_trm_ctx(&ohci->at_req_context);
initialize_dma_trm_ctx(&ohci->at_resp_context);
/* Accept AR requests from all nodes */
reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000);
/* Set the address range of the physical response unit.
* Most controllers do not implement it as a writable register though.
* They will keep a hardwired offset of 0x00010000 and show 0x0 as
* register content.
* To actually enable physical responses is the job of our interrupt
* handler which programs the physical request filter. */
reg_write(ohci, OHCI1394_PhyUpperBound,
OHCI1394_PHYS_UPPER_BOUND_PROGRAMMED >> 16);
DBGMSG("physUpperBoundOffset=%08x",
reg_read(ohci, OHCI1394_PhyUpperBound));
/* Specify AT retries */
reg_write(ohci, OHCI1394_ATRetries,
OHCI1394_MAX_AT_REQ_RETRIES |
(OHCI1394_MAX_AT_RESP_RETRIES<<4) |
(OHCI1394_MAX_PHYS_RESP_RETRIES<<8));
/* We don't want hardware swapping */
reg_write(ohci, OHCI1394_HCControlClear, OHCI1394_HCControl_noByteSwap);
/* Enable interrupts */
reg_write(ohci, OHCI1394_IntMaskSet,
OHCI1394_unrecoverableError |
OHCI1394_masterIntEnable |
OHCI1394_busReset |
OHCI1394_selfIDComplete |
OHCI1394_RSPkt |
OHCI1394_RQPkt |
OHCI1394_respTxComplete |
OHCI1394_reqTxComplete |
OHCI1394_isochRx |
OHCI1394_isochTx |
OHCI1394_postedWriteErr |
OHCI1394_cycleTooLong |
OHCI1394_cycleInconsistent);
/* Enable link */
reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_linkEnable);
buf = reg_read(ohci, OHCI1394_Version);
PRINT(KERN_INFO, "OHCI-1394 %d.%d (PCI): IRQ=[%d] "
"MMIO=[%llx-%llx] Max Packet=[%d] IR/IT contexts=[%d/%d]",
((((buf) >> 16) & 0xf) + (((buf) >> 20) & 0xf) * 10),
((((buf) >> 4) & 0xf) + ((buf) & 0xf) * 10), ohci->dev->irq,
(unsigned long long)pci_resource_start(ohci->dev, 0),
(unsigned long long)pci_resource_start(ohci->dev, 0) + OHCI1394_REGISTER_SIZE - 1,
ohci->max_packet_size,
ohci->nb_iso_rcv_ctx, ohci->nb_iso_xmit_ctx);
/* Check all of our ports to make sure that if anything is
* connected, we enable that port. */
num_ports = get_phy_reg(ohci, 2) & 0xf;
for (i = 0; i < num_ports; i++) {
unsigned int status;
set_phy_reg(ohci, 7, i);
status = get_phy_reg(ohci, 8);
if (status & 0x20)
set_phy_reg(ohci, 8, status & ~1);
}
/* Serial EEPROM Sanity check. */
if ((ohci->max_packet_size < 512) ||
(ohci->max_packet_size > 4096)) {
/* Serial EEPROM contents are suspect, set a sane max packet
* size and print the raw contents for bug reports if verbose
* debug is enabled. */
#ifdef CONFIG_IEEE1394_VERBOSEDEBUG
int i;
#endif
PRINT(KERN_DEBUG, "Serial EEPROM has suspicious values, "
"attempting to set max_packet_size to 512 bytes");
reg_write(ohci, OHCI1394_BusOptions,
(reg_read(ohci, OHCI1394_BusOptions) & 0xf007) | 0x8002);
ohci->max_packet_size = 512;
#ifdef CONFIG_IEEE1394_VERBOSEDEBUG
PRINT(KERN_DEBUG, " EEPROM Present: %d",
(reg_read(ohci, OHCI1394_Version) >> 24) & 0x1);
reg_write(ohci, OHCI1394_GUID_ROM, 0x80000000);
for (i = 0;
((i < 1000) &&
(reg_read(ohci, OHCI1394_GUID_ROM) & 0x80000000)); i++)
udelay(10);
for (i = 0; i < 0x20; i++) {
reg_write(ohci, OHCI1394_GUID_ROM, 0x02000000);
PRINT(KERN_DEBUG, " EEPROM %02x: %02x", i,
(reg_read(ohci, OHCI1394_GUID_ROM) >> 16) & 0xff);
}
#endif
}
}
/*
* Insert a packet in the DMA fifo and generate the DMA prg
* FIXME: rewrite the program in order to accept packets crossing
* page boundaries.
* check also that a single dma descriptor doesn't cross a
* page boundary.
*/
static void insert_packet(struct ti_ohci *ohci,
struct dma_trm_ctx *d, struct hpsb_packet *packet)
{
u32 cycleTimer;
int idx = d->prg_ind;
DBGMSG("Inserting packet for node " NODE_BUS_FMT
", tlabel=%d, tcode=0x%x, speed=%d",
NODE_BUS_ARGS(ohci->host, packet->node_id), packet->tlabel,
packet->tcode, packet->speed_code);
d->prg_cpu[idx]->begin.address = 0;
d->prg_cpu[idx]->begin.branchAddress = 0;
if (d->type == DMA_CTX_ASYNC_RESP) {
/*
* For response packets, we need to put a timeout value in
* the 16 lower bits of the status... let's try 1 sec timeout
*/
cycleTimer = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
d->prg_cpu[idx]->begin.status = cpu_to_le32(
(((((cycleTimer>>25)&0x7)+1)&0x7)<<13) |
((cycleTimer&0x01fff000)>>12));
DBGMSG("cycleTimer: %08x timeStamp: %08x",
cycleTimer, d->prg_cpu[idx]->begin.status);
} else
d->prg_cpu[idx]->begin.status = 0;
if ( (packet->type == hpsb_async) || (packet->type == hpsb_raw) ) {
if (packet->type == hpsb_raw) {
d->prg_cpu[idx]->data[0] = cpu_to_le32(OHCI1394_TCODE_PHY<<4);
d->prg_cpu[idx]->data[1] = cpu_to_le32(packet->header[0]);
d->prg_cpu[idx]->data[2] = cpu_to_le32(packet->header[1]);
} else {
d->prg_cpu[idx]->data[0] = packet->speed_code<<16 |
(packet->header[0] & 0xFFFF);
if (packet->tcode == TCODE_ISO_DATA) {
/* Sending an async stream packet */
d->prg_cpu[idx]->data[1] = packet->header[0] & 0xFFFF0000;
} else {
/* Sending a normal async request or response */
d->prg_cpu[idx]->data[1] =
(packet->header[1] & 0xFFFF) |
(packet->header[0] & 0xFFFF0000);
d->prg_cpu[idx]->data[2] = packet->header[2];
d->prg_cpu[idx]->data[3] = packet->header[3];
}
header_le32_to_cpu(d->prg_cpu[idx]->data, packet->tcode);
}
if (packet->data_size) { /* block transmit */
if (packet->tcode == TCODE_STREAM_DATA){
d->prg_cpu[idx]->begin.control =
cpu_to_le32(DMA_CTL_OUTPUT_MORE |
DMA_CTL_IMMEDIATE | 0x8);
} else {
d->prg_cpu[idx]->begin.control =
cpu_to_le32(DMA_CTL_OUTPUT_MORE |
DMA_CTL_IMMEDIATE | 0x10);
}
d->prg_cpu[idx]->end.control =
cpu_to_le32(DMA_CTL_OUTPUT_LAST |
DMA_CTL_IRQ |
DMA_CTL_BRANCH |
packet->data_size);
/*
* Check that the packet data buffer
* does not cross a page boundary.
*
* XXX Fix this some day. eth1394 seems to trigger
* it, but ignoring it doesn't seem to cause a
* problem.
*/
#if 0
if (cross_bound((unsigned long)packet->data,
packet->data_size)>0) {
/* FIXME: do something about it */
PRINT(KERN_ERR,
"%s: packet data addr: %p size %Zd bytes "
"cross page boundary", __func__,
packet->data, packet->data_size);
}
#endif
d->prg_cpu[idx]->end.address = cpu_to_le32(
pci_map_single(ohci->dev, packet->data,
packet->data_size,
PCI_DMA_TODEVICE));
d->prg_cpu[idx]->end.branchAddress = 0;
d->prg_cpu[idx]->end.status = 0;
if (d->branchAddrPtr)
*(d->branchAddrPtr) =
cpu_to_le32(d->prg_bus[idx] | 0x3);
d->branchAddrPtr =
&(d->prg_cpu[idx]->end.branchAddress);
} else { /* quadlet transmit */
if (packet->type == hpsb_raw)
d->prg_cpu[idx]->begin.control =
cpu_to_le32(DMA_CTL_OUTPUT_LAST |
DMA_CTL_IMMEDIATE |
DMA_CTL_IRQ |
DMA_CTL_BRANCH |
(packet->header_size + 4));
else
d->prg_cpu[idx]->begin.control =
cpu_to_le32(DMA_CTL_OUTPUT_LAST |
DMA_CTL_IMMEDIATE |
DMA_CTL_IRQ |
DMA_CTL_BRANCH |
packet->header_size);
if (d->branchAddrPtr)
*(d->branchAddrPtr) =
cpu_to_le32(d->prg_bus[idx] | 0x2);
d->branchAddrPtr =
&(d->prg_cpu[idx]->begin.branchAddress);
}
} else { /* iso packet */
d->prg_cpu[idx]->data[0] = packet->speed_code<<16 |
(packet->header[0] & 0xFFFF);
d->prg_cpu[idx]->data[1] = packet->header[0] & 0xFFFF0000;
header_le32_to_cpu(d->prg_cpu[idx]->data, packet->tcode);
d->prg_cpu[idx]->begin.control =
cpu_to_le32(DMA_CTL_OUTPUT_MORE |
DMA_CTL_IMMEDIATE | 0x8);
d->prg_cpu[idx]->end.control =
cpu_to_le32(DMA_CTL_OUTPUT_LAST |
DMA_CTL_UPDATE |
DMA_CTL_IRQ |
DMA_CTL_BRANCH |
packet->data_size);
d->prg_cpu[idx]->end.address = cpu_to_le32(
pci_map_single(ohci->dev, packet->data,
packet->data_size, PCI_DMA_TODEVICE));
d->prg_cpu[idx]->end.branchAddress = 0;
d->prg_cpu[idx]->end.status = 0;
DBGMSG("Iso xmit context info: header[%08x %08x]\n"
" begin=%08x %08x %08x %08x\n"
" %08x %08x %08x %08x\n"
" end =%08x %08x %08x %08x",
d->prg_cpu[idx]->data[0], d->prg_cpu[idx]->data[1],
d->prg_cpu[idx]->begin.control,
d->prg_cpu[idx]->begin.address,
d->prg_cpu[idx]->begin.branchAddress,
d->prg_cpu[idx]->begin.status,
d->prg_cpu[idx]->data[0],
d->prg_cpu[idx]->data[1],
d->prg_cpu[idx]->data[2],
d->prg_cpu[idx]->data[3],
d->prg_cpu[idx]->end.control,
d->prg_cpu[idx]->end.address,
d->prg_cpu[idx]->end.branchAddress,
d->prg_cpu[idx]->end.status);
if (d->branchAddrPtr)
*(d->branchAddrPtr) = cpu_to_le32(d->prg_bus[idx] | 0x3);
d->branchAddrPtr = &(d->prg_cpu[idx]->end.branchAddress);
}
d->free_prgs--;
/* queue the packet in the appropriate context queue */
list_add_tail(&packet->driver_list, &d->fifo_list);
d->prg_ind = (d->prg_ind + 1) % d->num_desc;
}
/*
* This function fills the FIFO with the (eventual) pending packets
* and runs or wakes up the DMA prg if necessary.
*
* The function MUST be called with the d->lock held.
*/
static void dma_trm_flush(struct ti_ohci *ohci, struct dma_trm_ctx *d)
{
struct hpsb_packet *packet, *ptmp;
int idx = d->prg_ind;
int z = 0;
/* insert the packets into the dma fifo */
list_for_each_entry_safe(packet, ptmp, &d->pending_list, driver_list) {
if (!d->free_prgs)
break;
/* For the first packet only */
if (!z)
z = (packet->data_size) ? 3 : 2;
/* Insert the packet */
list_del_init(&packet->driver_list);
insert_packet(ohci, d, packet);
}
/* Nothing must have been done, either no free_prgs or no packets */
if (z == 0)
return;
/* Is the context running ? (should be unless it is
the first packet to be sent in this context) */
if (!(reg_read(ohci, d->ctrlSet) & 0x8000)) {
u32 nodeId = reg_read(ohci, OHCI1394_NodeID);
DBGMSG("Starting transmit DMA ctx=%d",d->ctx);
reg_write(ohci, d->cmdPtr, d->prg_bus[idx] | z);
/* Check that the node id is valid, and not 63 */
if (!(nodeId & 0x80000000) || (nodeId & 0x3f) == 63)
PRINT(KERN_ERR, "Running dma failed because Node ID is not valid");
else
reg_write(ohci, d->ctrlSet, 0x8000);
} else {
/* Wake up the dma context if necessary */
if (!(reg_read(ohci, d->ctrlSet) & 0x400))
DBGMSG("Waking transmit DMA ctx=%d",d->ctx);
/* do this always, to avoid race condition */
reg_write(ohci, d->ctrlSet, 0x1000);
}
return;
}
/* Transmission of an async or iso packet */
static int ohci_transmit(struct hpsb_host *host, struct hpsb_packet *packet)
{
struct ti_ohci *ohci = host->hostdata;
struct dma_trm_ctx *d;
unsigned long flags;
if (packet->data_size > ohci->max_packet_size) {
PRINT(KERN_ERR,
"Transmit packet size %Zd is too big",
packet->data_size);
return -EOVERFLOW;
}
if (packet->type == hpsb_raw)
d = &ohci->at_req_context;
else if ((packet->tcode & 0x02) && (packet->tcode != TCODE_ISO_DATA))
d = &ohci->at_resp_context;
else
d = &ohci->at_req_context;
spin_lock_irqsave(&d->lock,flags);
list_add_tail(&packet->driver_list, &d->pending_list);
dma_trm_flush(ohci, d);
spin_unlock_irqrestore(&d->lock,flags);
return 0;
}
static int ohci_devctl(struct hpsb_host *host, enum devctl_cmd cmd, int arg)
{
struct ti_ohci *ohci = host->hostdata;
int retval = 0, phy_reg;
switch (cmd) {
case RESET_BUS:
switch (arg) {
case SHORT_RESET:
phy_reg = get_phy_reg(ohci, 5);
phy_reg |= 0x40;
set_phy_reg(ohci, 5, phy_reg); /* set ISBR */
break;
case LONG_RESET:
phy_reg = get_phy_reg(ohci, 1);
phy_reg |= 0x40;
set_phy_reg(ohci, 1, phy_reg); /* set IBR */
break;
case SHORT_RESET_NO_FORCE_ROOT:
phy_reg = get_phy_reg(ohci, 1);
if (phy_reg & 0x80) {
phy_reg &= ~0x80;
set_phy_reg(ohci, 1, phy_reg); /* clear RHB */
}
phy_reg = get_phy_reg(ohci, 5);
phy_reg |= 0x40;
set_phy_reg(ohci, 5, phy_reg); /* set ISBR */
break;
case LONG_RESET_NO_FORCE_ROOT:
phy_reg = get_phy_reg(ohci, 1);
phy_reg &= ~0x80;
phy_reg |= 0x40;
set_phy_reg(ohci, 1, phy_reg); /* clear RHB, set IBR */
break;
case SHORT_RESET_FORCE_ROOT:
phy_reg = get_phy_reg(ohci, 1);
if (!(phy_reg & 0x80)) {
phy_reg |= 0x80;
set_phy_reg(ohci, 1, phy_reg); /* set RHB */
}
phy_reg = get_phy_reg(ohci, 5);
phy_reg |= 0x40;
set_phy_reg(ohci, 5, phy_reg); /* set ISBR */
break;
case LONG_RESET_FORCE_ROOT:
phy_reg = get_phy_reg(ohci, 1);
phy_reg |= 0xc0;
set_phy_reg(ohci, 1, phy_reg); /* set RHB and IBR */
break;
default:
retval = -1;
}
break;
case GET_CYCLE_COUNTER:
retval = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
break;
case SET_CYCLE_COUNTER:
reg_write(ohci, OHCI1394_IsochronousCycleTimer, arg);
break;
case SET_BUS_ID:
PRINT(KERN_ERR, "devctl command SET_BUS_ID err");
break;
case ACT_CYCLE_MASTER:
if (arg) {
/* check if we are root and other nodes are present */
u32 nodeId = reg_read(ohci, OHCI1394_NodeID);
if ((nodeId & (1<<30)) && (nodeId & 0x3f)) {
/*
* enable cycleTimer, cycleMaster
*/
DBGMSG("Cycle master enabled");
reg_write(ohci, OHCI1394_LinkControlSet,
OHCI1394_LinkControl_CycleTimerEnable |
OHCI1394_LinkControl_CycleMaster);
}
} else {
/* disable cycleTimer, cycleMaster, cycleSource */
reg_write(ohci, OHCI1394_LinkControlClear,
OHCI1394_LinkControl_CycleTimerEnable |
OHCI1394_LinkControl_CycleMaster |
OHCI1394_LinkControl_CycleSource);
}
break;
case CANCEL_REQUESTS:
DBGMSG("Cancel request received");
dma_trm_reset(&ohci->at_req_context);
dma_trm_reset(&ohci->at_resp_context);
break;
default:
PRINT_G(KERN_ERR, "ohci_devctl cmd %d not implemented yet",
cmd);
break;
}
return retval;
}
/***********************************
* rawiso ISO reception *
***********************************/
/*
We use either buffer-fill or packet-per-buffer DMA mode. The DMA
buffer is split into "blocks" (regions described by one DMA
descriptor). Each block must be one page or less in size, and
must not cross a page boundary.
There is one little wrinkle with buffer-fill mode: a packet that
starts in the final block may wrap around into the first block. But
the user API expects all packets to be contiguous. Our solution is
to keep the very last page of the DMA buffer in reserve - if a
packet spans the gap, we copy its tail into this page.