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rtc-ds1685.c
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rtc-ds1685.c
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/*
* An rtc driver for the Dallas/Maxim DS1685/DS1687 and related real-time
* chips.
*
* Copyright (C) 2011-2014 Joshua Kinard <[email protected]>.
* Copyright (C) 2009 Matthias Fuchs <[email protected]>.
*
* References:
* DS1685/DS1687 3V/5V Real-Time Clocks, 19-5215, Rev 4/10.
* DS17x85/DS17x87 3V/5V Real-Time Clocks, 19-5222, Rev 4/10.
* DS1689/DS1693 3V/5V Serialized Real-Time Clocks, Rev 112105.
* Application Note 90, Using the Multiplex Bus RTC Extended Features.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/bcd.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/rtc.h>
#include <linux/workqueue.h>
#include <linux/rtc/ds1685.h>
#ifdef CONFIG_PROC_FS
#include <linux/proc_fs.h>
#endif
#define DRV_VERSION "0.42.0"
/* ----------------------------------------------------------------------- */
/* Standard read/write functions if platform does not provide overrides */
/**
* ds1685_read - read a value from an rtc register.
* @rtc: pointer to the ds1685 rtc structure.
* @reg: the register address to read.
*/
static u8
ds1685_read(struct ds1685_priv *rtc, int reg)
{
return readb((u8 __iomem *)rtc->regs +
(reg * rtc->regstep));
}
/**
* ds1685_write - write a value to an rtc register.
* @rtc: pointer to the ds1685 rtc structure.
* @reg: the register address to write.
* @value: value to write to the register.
*/
static void
ds1685_write(struct ds1685_priv *rtc, int reg, u8 value)
{
writeb(value, ((u8 __iomem *)rtc->regs +
(reg * rtc->regstep)));
}
/* ----------------------------------------------------------------------- */
/* ----------------------------------------------------------------------- */
/* Inlined functions */
/**
* ds1685_rtc_bcd2bin - bcd2bin wrapper in case platform doesn't support BCD.
* @rtc: pointer to the ds1685 rtc structure.
* @val: u8 time value to consider converting.
* @bcd_mask: u8 mask value if BCD mode is used.
* @bin_mask: u8 mask value if BIN mode is used.
*
* Returns the value, converted to BIN if originally in BCD and bcd_mode TRUE.
*/
static inline u8
ds1685_rtc_bcd2bin(struct ds1685_priv *rtc, u8 val, u8 bcd_mask, u8 bin_mask)
{
if (rtc->bcd_mode)
return (bcd2bin(val) & bcd_mask);
return (val & bin_mask);
}
/**
* ds1685_rtc_bin2bcd - bin2bcd wrapper in case platform doesn't support BCD.
* @rtc: pointer to the ds1685 rtc structure.
* @val: u8 time value to consider converting.
* @bin_mask: u8 mask value if BIN mode is used.
* @bcd_mask: u8 mask value if BCD mode is used.
*
* Returns the value, converted to BCD if originally in BIN and bcd_mode TRUE.
*/
static inline u8
ds1685_rtc_bin2bcd(struct ds1685_priv *rtc, u8 val, u8 bin_mask, u8 bcd_mask)
{
if (rtc->bcd_mode)
return (bin2bcd(val) & bcd_mask);
return (val & bin_mask);
}
/**
* ds1685_rtc_switch_to_bank0 - switch the rtc to bank 0.
* @rtc: pointer to the ds1685 rtc structure.
*/
static inline void
ds1685_rtc_switch_to_bank0(struct ds1685_priv *rtc)
{
rtc->write(rtc, RTC_CTRL_A,
(rtc->read(rtc, RTC_CTRL_A) & ~(RTC_CTRL_A_DV0)));
}
/**
* ds1685_rtc_switch_to_bank1 - switch the rtc to bank 1.
* @rtc: pointer to the ds1685 rtc structure.
*/
static inline void
ds1685_rtc_switch_to_bank1(struct ds1685_priv *rtc)
{
rtc->write(rtc, RTC_CTRL_A,
(rtc->read(rtc, RTC_CTRL_A) | RTC_CTRL_A_DV0));
}
/**
* ds1685_rtc_begin_data_access - prepare the rtc for data access.
* @rtc: pointer to the ds1685 rtc structure.
*
* This takes several steps to prepare the rtc for access to get/set time
* and alarm values from the rtc registers:
* - Sets the SET bit in Control Register B.
* - Reads Ext Control Register 4A and checks the INCR bit.
* - If INCR is active, a short delay is added before Ext Control Register 4A
* is read again in a loop until INCR is inactive.
* - Switches the rtc to bank 1. This allows access to all relevant
* data for normal rtc operation, as bank 0 contains only the nvram.
*/
static inline void
ds1685_rtc_begin_data_access(struct ds1685_priv *rtc)
{
/* Set the SET bit in Ctrl B */
rtc->write(rtc, RTC_CTRL_B,
(rtc->read(rtc, RTC_CTRL_B) | RTC_CTRL_B_SET));
/* Read Ext Ctrl 4A and check the INCR bit to avoid a lockout. */
while (rtc->read(rtc, RTC_EXT_CTRL_4A) & RTC_CTRL_4A_INCR)
cpu_relax();
/* Switch to Bank 1 */
ds1685_rtc_switch_to_bank1(rtc);
}
/**
* ds1685_rtc_end_data_access - end data access on the rtc.
* @rtc: pointer to the ds1685 rtc structure.
*
* This ends what was started by ds1685_rtc_begin_data_access:
* - Switches the rtc back to bank 0.
* - Clears the SET bit in Control Register B.
*/
static inline void
ds1685_rtc_end_data_access(struct ds1685_priv *rtc)
{
/* Switch back to Bank 0 */
ds1685_rtc_switch_to_bank1(rtc);
/* Clear the SET bit in Ctrl B */
rtc->write(rtc, RTC_CTRL_B,
(rtc->read(rtc, RTC_CTRL_B) & ~(RTC_CTRL_B_SET)));
}
/**
* ds1685_rtc_begin_ctrl_access - prepare the rtc for ctrl access.
* @rtc: pointer to the ds1685 rtc structure.
* @flags: irq flags variable for spin_lock_irqsave.
*
* This takes several steps to prepare the rtc for access to read just the
* control registers:
* - Sets a spinlock on the rtc IRQ.
* - Switches the rtc to bank 1. This allows access to the two extended
* control registers.
*
* Only use this where you are certain another lock will not be held.
*/
static inline void
ds1685_rtc_begin_ctrl_access(struct ds1685_priv *rtc, unsigned long *flags)
{
spin_lock_irqsave(&rtc->lock, *flags);
ds1685_rtc_switch_to_bank1(rtc);
}
/**
* ds1685_rtc_end_ctrl_access - end ctrl access on the rtc.
* @rtc: pointer to the ds1685 rtc structure.
* @flags: irq flags variable for spin_unlock_irqrestore.
*
* This ends what was started by ds1685_rtc_begin_ctrl_access:
* - Switches the rtc back to bank 0.
* - Unsets the spinlock on the rtc IRQ.
*/
static inline void
ds1685_rtc_end_ctrl_access(struct ds1685_priv *rtc, unsigned long flags)
{
ds1685_rtc_switch_to_bank0(rtc);
spin_unlock_irqrestore(&rtc->lock, flags);
}
/**
* ds1685_rtc_get_ssn - retrieve the silicon serial number.
* @rtc: pointer to the ds1685 rtc structure.
* @ssn: u8 array to hold the bits of the silicon serial number.
*
* This number starts at 0x40, and is 8-bytes long, ending at 0x47. The
* first byte is the model number, the next six bytes are the serial number
* digits, and the final byte is a CRC check byte. Together, they form the
* silicon serial number.
*
* These values are stored in bank1, so ds1685_rtc_switch_to_bank1 must be
* called first before calling this function, else data will be read out of
* the bank0 NVRAM. Be sure to call ds1685_rtc_switch_to_bank0 when done.
*/
static inline void
ds1685_rtc_get_ssn(struct ds1685_priv *rtc, u8 *ssn)
{
ssn[0] = rtc->read(rtc, RTC_BANK1_SSN_MODEL);
ssn[1] = rtc->read(rtc, RTC_BANK1_SSN_BYTE_1);
ssn[2] = rtc->read(rtc, RTC_BANK1_SSN_BYTE_2);
ssn[3] = rtc->read(rtc, RTC_BANK1_SSN_BYTE_3);
ssn[4] = rtc->read(rtc, RTC_BANK1_SSN_BYTE_4);
ssn[5] = rtc->read(rtc, RTC_BANK1_SSN_BYTE_5);
ssn[6] = rtc->read(rtc, RTC_BANK1_SSN_BYTE_6);
ssn[7] = rtc->read(rtc, RTC_BANK1_SSN_CRC);
}
/* ----------------------------------------------------------------------- */
/* ----------------------------------------------------------------------- */
/* Read/Set Time & Alarm functions */
/**
* ds1685_rtc_read_time - reads the time registers.
* @dev: pointer to device structure.
* @tm: pointer to rtc_time structure.
*/
static int
ds1685_rtc_read_time(struct device *dev, struct rtc_time *tm)
{
struct platform_device *pdev = to_platform_device(dev);
struct ds1685_priv *rtc = platform_get_drvdata(pdev);
u8 ctrlb, century;
u8 seconds, minutes, hours, wday, mday, month, years;
/* Fetch the time info from the RTC registers. */
ds1685_rtc_begin_data_access(rtc);
seconds = rtc->read(rtc, RTC_SECS);
minutes = rtc->read(rtc, RTC_MINS);
hours = rtc->read(rtc, RTC_HRS);
wday = rtc->read(rtc, RTC_WDAY);
mday = rtc->read(rtc, RTC_MDAY);
month = rtc->read(rtc, RTC_MONTH);
years = rtc->read(rtc, RTC_YEAR);
century = rtc->read(rtc, RTC_CENTURY);
ctrlb = rtc->read(rtc, RTC_CTRL_B);
ds1685_rtc_end_data_access(rtc);
/* bcd2bin if needed, perform fixups, and store to rtc_time. */
years = ds1685_rtc_bcd2bin(rtc, years, RTC_YEAR_BCD_MASK,
RTC_YEAR_BIN_MASK);
century = ds1685_rtc_bcd2bin(rtc, century, RTC_CENTURY_MASK,
RTC_CENTURY_MASK);
tm->tm_sec = ds1685_rtc_bcd2bin(rtc, seconds, RTC_SECS_BCD_MASK,
RTC_SECS_BIN_MASK);
tm->tm_min = ds1685_rtc_bcd2bin(rtc, minutes, RTC_MINS_BCD_MASK,
RTC_MINS_BIN_MASK);
tm->tm_hour = ds1685_rtc_bcd2bin(rtc, hours, RTC_HRS_24_BCD_MASK,
RTC_HRS_24_BIN_MASK);
tm->tm_wday = (ds1685_rtc_bcd2bin(rtc, wday, RTC_WDAY_MASK,
RTC_WDAY_MASK) - 1);
tm->tm_mday = ds1685_rtc_bcd2bin(rtc, mday, RTC_MDAY_BCD_MASK,
RTC_MDAY_BIN_MASK);
tm->tm_mon = (ds1685_rtc_bcd2bin(rtc, month, RTC_MONTH_BCD_MASK,
RTC_MONTH_BIN_MASK) - 1);
tm->tm_year = ((years + (century * 100)) - 1900);
tm->tm_yday = rtc_year_days(tm->tm_mday, tm->tm_mon, tm->tm_year);
tm->tm_isdst = 0; /* RTC has hardcoded timezone, so don't use. */
return rtc_valid_tm(tm);
}
/**
* ds1685_rtc_set_time - sets the time registers.
* @dev: pointer to device structure.
* @tm: pointer to rtc_time structure.
*/
static int
ds1685_rtc_set_time(struct device *dev, struct rtc_time *tm)
{
struct platform_device *pdev = to_platform_device(dev);
struct ds1685_priv *rtc = platform_get_drvdata(pdev);
u8 ctrlb, seconds, minutes, hours, wday, mday, month, years, century;
/* Fetch the time info from rtc_time. */
seconds = ds1685_rtc_bin2bcd(rtc, tm->tm_sec, RTC_SECS_BIN_MASK,
RTC_SECS_BCD_MASK);
minutes = ds1685_rtc_bin2bcd(rtc, tm->tm_min, RTC_MINS_BIN_MASK,
RTC_MINS_BCD_MASK);
hours = ds1685_rtc_bin2bcd(rtc, tm->tm_hour, RTC_HRS_24_BIN_MASK,
RTC_HRS_24_BCD_MASK);
wday = ds1685_rtc_bin2bcd(rtc, (tm->tm_wday + 1), RTC_WDAY_MASK,
RTC_WDAY_MASK);
mday = ds1685_rtc_bin2bcd(rtc, tm->tm_mday, RTC_MDAY_BIN_MASK,
RTC_MDAY_BCD_MASK);
month = ds1685_rtc_bin2bcd(rtc, (tm->tm_mon + 1), RTC_MONTH_BIN_MASK,
RTC_MONTH_BCD_MASK);
years = ds1685_rtc_bin2bcd(rtc, (tm->tm_year % 100),
RTC_YEAR_BIN_MASK, RTC_YEAR_BCD_MASK);
century = ds1685_rtc_bin2bcd(rtc, ((tm->tm_year + 1900) / 100),
RTC_CENTURY_MASK, RTC_CENTURY_MASK);
/*
* Perform Sanity Checks:
* - Months: !> 12, Month Day != 0.
* - Month Day !> Max days in current month.
* - Hours !>= 24, Mins !>= 60, Secs !>= 60, & Weekday !> 7.
*/
if ((tm->tm_mon > 11) || (mday == 0))
return -EDOM;
if (tm->tm_mday > rtc_month_days(tm->tm_mon, tm->tm_year))
return -EDOM;
if ((tm->tm_hour >= 24) || (tm->tm_min >= 60) ||
(tm->tm_sec >= 60) || (wday > 7))
return -EDOM;
/*
* Set the data mode to use and store the time values in the
* RTC registers.
*/
ds1685_rtc_begin_data_access(rtc);
ctrlb = rtc->read(rtc, RTC_CTRL_B);
if (rtc->bcd_mode)
ctrlb &= ~(RTC_CTRL_B_DM);
else
ctrlb |= RTC_CTRL_B_DM;
rtc->write(rtc, RTC_CTRL_B, ctrlb);
rtc->write(rtc, RTC_SECS, seconds);
rtc->write(rtc, RTC_MINS, minutes);
rtc->write(rtc, RTC_HRS, hours);
rtc->write(rtc, RTC_WDAY, wday);
rtc->write(rtc, RTC_MDAY, mday);
rtc->write(rtc, RTC_MONTH, month);
rtc->write(rtc, RTC_YEAR, years);
rtc->write(rtc, RTC_CENTURY, century);
ds1685_rtc_end_data_access(rtc);
return 0;
}
/**
* ds1685_rtc_read_alarm - reads the alarm registers.
* @dev: pointer to device structure.
* @alrm: pointer to rtc_wkalrm structure.
*
* There are three primary alarm registers: seconds, minutes, and hours.
* A fourth alarm register for the month date is also available in bank1 for
* kickstart/wakeup features. The DS1685/DS1687 manual states that a
* "don't care" value ranging from 0xc0 to 0xff may be written into one or
* more of the three alarm bytes to act as a wildcard value. The fourth
* byte doesn't support a "don't care" value.
*/
static int
ds1685_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
struct platform_device *pdev = to_platform_device(dev);
struct ds1685_priv *rtc = platform_get_drvdata(pdev);
u8 seconds, minutes, hours, mday, ctrlb, ctrlc;
/* Fetch the alarm info from the RTC alarm registers. */
ds1685_rtc_begin_data_access(rtc);
seconds = rtc->read(rtc, RTC_SECS_ALARM);
minutes = rtc->read(rtc, RTC_MINS_ALARM);
hours = rtc->read(rtc, RTC_HRS_ALARM);
mday = rtc->read(rtc, RTC_MDAY_ALARM);
ctrlb = rtc->read(rtc, RTC_CTRL_B);
ctrlc = rtc->read(rtc, RTC_CTRL_C);
ds1685_rtc_end_data_access(rtc);
/* Check month date. */
if (!(mday >= 1) && (mday <= 31))
return -EDOM;
/*
* Check the three alarm bytes.
*
* The Linux RTC system doesn't support the "don't care" capability
* of this RTC chip. We check for it anyways in case support is
* added in the future.
*/
if (unlikely(seconds >= 0xc0))
alrm->time.tm_sec = -1;
else
alrm->time.tm_sec = ds1685_rtc_bcd2bin(rtc, seconds,
RTC_SECS_BCD_MASK,
RTC_SECS_BIN_MASK);
if (unlikely(minutes >= 0xc0))
alrm->time.tm_min = -1;
else
alrm->time.tm_min = ds1685_rtc_bcd2bin(rtc, minutes,
RTC_MINS_BCD_MASK,
RTC_MINS_BIN_MASK);
if (unlikely(hours >= 0xc0))
alrm->time.tm_hour = -1;
else
alrm->time.tm_hour = ds1685_rtc_bcd2bin(rtc, hours,
RTC_HRS_24_BCD_MASK,
RTC_HRS_24_BIN_MASK);
/* Write the data to rtc_wkalrm. */
alrm->time.tm_mday = ds1685_rtc_bcd2bin(rtc, mday, RTC_MDAY_BCD_MASK,
RTC_MDAY_BIN_MASK);
alrm->time.tm_mon = -1;
alrm->time.tm_year = -1;
alrm->time.tm_wday = -1;
alrm->time.tm_yday = -1;
alrm->time.tm_isdst = -1;
alrm->enabled = !!(ctrlb & RTC_CTRL_B_AIE);
alrm->pending = !!(ctrlc & RTC_CTRL_C_AF);
return 0;
}
/**
* ds1685_rtc_set_alarm - sets the alarm in registers.
* @dev: pointer to device structure.
* @alrm: pointer to rtc_wkalrm structure.
*/
static int
ds1685_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
struct platform_device *pdev = to_platform_device(dev);
struct ds1685_priv *rtc = platform_get_drvdata(pdev);
u8 ctrlb, seconds, minutes, hours, mday;
/* Fetch the alarm info and convert to BCD. */
seconds = ds1685_rtc_bin2bcd(rtc, alrm->time.tm_sec,
RTC_SECS_BIN_MASK,
RTC_SECS_BCD_MASK);
minutes = ds1685_rtc_bin2bcd(rtc, alrm->time.tm_min,
RTC_MINS_BIN_MASK,
RTC_MINS_BCD_MASK);
hours = ds1685_rtc_bin2bcd(rtc, alrm->time.tm_hour,
RTC_HRS_24_BIN_MASK,
RTC_HRS_24_BCD_MASK);
mday = ds1685_rtc_bin2bcd(rtc, alrm->time.tm_mday,
RTC_MDAY_BIN_MASK,
RTC_MDAY_BCD_MASK);
/* Check the month date for validity. */
if (!(mday >= 1) && (mday <= 31))
return -EDOM;
/*
* Check the three alarm bytes.
*
* The Linux RTC system doesn't support the "don't care" capability
* of this RTC chip because rtc_valid_tm tries to validate every
* field, and we only support four fields. We put the support
* here anyways for the future.
*/
if (unlikely(seconds >= 0xc0))
seconds = 0xff;
if (unlikely(minutes >= 0xc0))
minutes = 0xff;
if (unlikely(hours >= 0xc0))
hours = 0xff;
alrm->time.tm_mon = -1;
alrm->time.tm_year = -1;
alrm->time.tm_wday = -1;
alrm->time.tm_yday = -1;
alrm->time.tm_isdst = -1;
/* Disable the alarm interrupt first. */
ds1685_rtc_begin_data_access(rtc);
ctrlb = rtc->read(rtc, RTC_CTRL_B);
rtc->write(rtc, RTC_CTRL_B, (ctrlb & ~(RTC_CTRL_B_AIE)));
/* Read ctrlc to clear RTC_CTRL_C_AF. */
rtc->read(rtc, RTC_CTRL_C);
/*
* Set the data mode to use and store the time values in the
* RTC registers.
*/
ctrlb = rtc->read(rtc, RTC_CTRL_B);
if (rtc->bcd_mode)
ctrlb &= ~(RTC_CTRL_B_DM);
else
ctrlb |= RTC_CTRL_B_DM;
rtc->write(rtc, RTC_CTRL_B, ctrlb);
rtc->write(rtc, RTC_SECS_ALARM, seconds);
rtc->write(rtc, RTC_MINS_ALARM, minutes);
rtc->write(rtc, RTC_HRS_ALARM, hours);
rtc->write(rtc, RTC_MDAY_ALARM, mday);
/* Re-enable the alarm if needed. */
if (alrm->enabled) {
ctrlb = rtc->read(rtc, RTC_CTRL_B);
ctrlb |= RTC_CTRL_B_AIE;
rtc->write(rtc, RTC_CTRL_B, ctrlb);
}
/* Done! */
ds1685_rtc_end_data_access(rtc);
return 0;
}
/* ----------------------------------------------------------------------- */
/* ----------------------------------------------------------------------- */
/* /dev/rtcX Interface functions */
/**
* ds1685_rtc_alarm_irq_enable - replaces ioctl() RTC_AIE on/off.
* @dev: pointer to device structure.
* @enabled: flag indicating whether to enable or disable.
*/
static int
ds1685_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
{
struct ds1685_priv *rtc = dev_get_drvdata(dev);
unsigned long flags = 0;
/* Enable/disable the Alarm IRQ-Enable flag. */
spin_lock_irqsave(&rtc->lock, flags);
/* Flip the requisite interrupt-enable bit. */
if (enabled)
rtc->write(rtc, RTC_CTRL_B, (rtc->read(rtc, RTC_CTRL_B) |
RTC_CTRL_B_AIE));
else
rtc->write(rtc, RTC_CTRL_B, (rtc->read(rtc, RTC_CTRL_B) &
~(RTC_CTRL_B_AIE)));
/* Read Control C to clear all the flag bits. */
rtc->read(rtc, RTC_CTRL_C);
spin_unlock_irqrestore(&rtc->lock, flags);
return 0;
}
/* ----------------------------------------------------------------------- */
/* ----------------------------------------------------------------------- */
/* IRQ handler & workqueue. */
/**
* ds1685_rtc_irq_handler - IRQ handler.
* @irq: IRQ number.
* @dev_id: platform device pointer.
*/
static irqreturn_t
ds1685_rtc_irq_handler(int irq, void *dev_id)
{
struct platform_device *pdev = dev_id;
struct ds1685_priv *rtc = platform_get_drvdata(pdev);
u8 ctrlb, ctrlc;
unsigned long events = 0;
u8 num_irqs = 0;
/* Abort early if the device isn't ready yet (i.e., DEBUG_SHIRQ). */
if (unlikely(!rtc))
return IRQ_HANDLED;
/* Ctrlb holds the interrupt-enable bits and ctrlc the flag bits. */
spin_lock(&rtc->lock);
ctrlb = rtc->read(rtc, RTC_CTRL_B);
ctrlc = rtc->read(rtc, RTC_CTRL_C);
/* Is the IRQF bit set? */
if (likely(ctrlc & RTC_CTRL_C_IRQF)) {
/*
* We need to determine if it was one of the standard
* events: PF, AF, or UF. If so, we handle them and
* update the RTC core.
*/
if (likely(ctrlc & RTC_CTRL_B_PAU_MASK)) {
events = RTC_IRQF;
/* Check for a periodic interrupt. */
if ((ctrlb & RTC_CTRL_B_PIE) &&
(ctrlc & RTC_CTRL_C_PF)) {
events |= RTC_PF;
num_irqs++;
}
/* Check for an alarm interrupt. */
if ((ctrlb & RTC_CTRL_B_AIE) &&
(ctrlc & RTC_CTRL_C_AF)) {
events |= RTC_AF;
num_irqs++;
}
/* Check for an update interrupt. */
if ((ctrlb & RTC_CTRL_B_UIE) &&
(ctrlc & RTC_CTRL_C_UF)) {
events |= RTC_UF;
num_irqs++;
}
rtc_update_irq(rtc->dev, num_irqs, events);
} else {
/*
* One of the "extended" interrupts was received that
* is not recognized by the RTC core. These need to
* be handled in task context as they can call other
* functions and the time spent in irq context needs
* to be minimized. Schedule them into a workqueue
* and inform the RTC core that the IRQs were handled.
*/
spin_unlock(&rtc->lock);
schedule_work(&rtc->work);
rtc_update_irq(rtc->dev, 0, 0);
return IRQ_HANDLED;
}
}
spin_unlock(&rtc->lock);
return events ? IRQ_HANDLED : IRQ_NONE;
}
/**
* ds1685_rtc_work_queue - work queue handler.
* @work: work_struct containing data to work on in task context.
*/
static void
ds1685_rtc_work_queue(struct work_struct *work)
{
struct ds1685_priv *rtc = container_of(work,
struct ds1685_priv, work);
struct platform_device *pdev = to_platform_device(&rtc->dev->dev);
struct mutex *rtc_mutex = &rtc->dev->ops_lock;
u8 ctrl4a, ctrl4b;
mutex_lock(rtc_mutex);
ds1685_rtc_switch_to_bank1(rtc);
ctrl4a = rtc->read(rtc, RTC_EXT_CTRL_4A);
ctrl4b = rtc->read(rtc, RTC_EXT_CTRL_4B);
/*
* Check for a kickstart interrupt. With Vcc applied, this
* typically means that the power button was pressed, so we
* begin the shutdown sequence.
*/
if ((ctrl4b & RTC_CTRL_4B_KSE) && (ctrl4a & RTC_CTRL_4A_KF)) {
/* Briefly disable kickstarts to debounce button presses. */
rtc->write(rtc, RTC_EXT_CTRL_4B,
(rtc->read(rtc, RTC_EXT_CTRL_4B) &
~(RTC_CTRL_4B_KSE)));
/* Clear the kickstart flag. */
rtc->write(rtc, RTC_EXT_CTRL_4A,
(ctrl4a & ~(RTC_CTRL_4A_KF)));
/*
* Sleep 500ms before re-enabling kickstarts. This allows
* adequate time to avoid reading signal jitter as additional
* button presses.
*/
msleep(500);
rtc->write(rtc, RTC_EXT_CTRL_4B,
(rtc->read(rtc, RTC_EXT_CTRL_4B) |
RTC_CTRL_4B_KSE));
/* Call the platform pre-poweroff function. Else, shutdown. */
if (rtc->prepare_poweroff != NULL)
rtc->prepare_poweroff();
else
ds1685_rtc_poweroff(pdev);
}
/*
* Check for a wake-up interrupt. With Vcc applied, this is
* essentially a second alarm interrupt, except it takes into
* account the 'date' register in bank1 in addition to the
* standard three alarm registers.
*/
if ((ctrl4b & RTC_CTRL_4B_WIE) && (ctrl4a & RTC_CTRL_4A_WF)) {
rtc->write(rtc, RTC_EXT_CTRL_4A,
(ctrl4a & ~(RTC_CTRL_4A_WF)));
/* Call the platform wake_alarm function if defined. */
if (rtc->wake_alarm != NULL)
rtc->wake_alarm();
else
dev_warn(&pdev->dev,
"Wake Alarm IRQ just occurred!\n");
}
/*
* Check for a ram-clear interrupt. This happens if RIE=1 and RF=0
* when RCE=1 in 4B. This clears all NVRAM bytes in bank0 by setting
* each byte to a logic 1. This has no effect on any extended
* NV-SRAM that might be present, nor on the time/calendar/alarm
* registers. After a ram-clear is completed, there is a minimum
* recovery time of ~150ms in which all reads/writes are locked out.
* NOTE: A ram-clear can still occur if RCE=1 and RIE=0. We cannot
* catch this scenario.
*/
if ((ctrl4b & RTC_CTRL_4B_RIE) && (ctrl4a & RTC_CTRL_4A_RF)) {
rtc->write(rtc, RTC_EXT_CTRL_4A,
(ctrl4a & ~(RTC_CTRL_4A_RF)));
msleep(150);
/* Call the platform post_ram_clear function if defined. */
if (rtc->post_ram_clear != NULL)
rtc->post_ram_clear();
else
dev_warn(&pdev->dev,
"RAM-Clear IRQ just occurred!\n");
}
ds1685_rtc_switch_to_bank0(rtc);
mutex_unlock(rtc_mutex);
}
/* ----------------------------------------------------------------------- */
/* ----------------------------------------------------------------------- */
/* ProcFS interface */
#ifdef CONFIG_PROC_FS
#define NUM_REGS 6 /* Num of control registers. */
#define NUM_BITS 8 /* Num bits per register. */
#define NUM_SPACES 4 /* Num spaces between each bit. */
/*
* Periodic Interrupt Rates.
*/
static const char *ds1685_rtc_pirq_rate[16] = {
"none", "3.90625ms", "7.8125ms", "0.122070ms", "0.244141ms",
"0.488281ms", "0.9765625ms", "1.953125ms", "3.90625ms", "7.8125ms",
"15.625ms", "31.25ms", "62.5ms", "125ms", "250ms", "500ms"
};
/*
* Square-Wave Output Frequencies.
*/
static const char *ds1685_rtc_sqw_freq[16] = {
"none", "256Hz", "128Hz", "8192Hz", "4096Hz", "2048Hz", "1024Hz",
"512Hz", "256Hz", "128Hz", "64Hz", "32Hz", "16Hz", "8Hz", "4Hz", "2Hz"
};
#ifdef CONFIG_RTC_DS1685_PROC_REGS
/**
* ds1685_rtc_print_regs - helper function to print register values.
* @hex: hex byte to convert into binary bits.
* @dest: destination char array.
*
* This is basically a hex->binary function, just with extra spacing between
* the digits. It only works on 1-byte values (8 bits).
*/
static char*
ds1685_rtc_print_regs(u8 hex, char *dest)
{
u32 i, j;
char *tmp = dest;
for (i = 0; i < NUM_BITS; i++) {
*tmp++ = ((hex & 0x80) != 0 ? '1' : '0');
for (j = 0; j < NUM_SPACES; j++)
*tmp++ = ' ';
hex <<= 1;
}
*tmp++ = '\0';
return dest;
}
#endif
/**
* ds1685_rtc_proc - procfs access function.
* @dev: pointer to device structure.
* @seq: pointer to seq_file structure.
*/
static int
ds1685_rtc_proc(struct device *dev, struct seq_file *seq)
{
struct platform_device *pdev = to_platform_device(dev);
struct ds1685_priv *rtc = platform_get_drvdata(pdev);
u8 ctrla, ctrlb, ctrlc, ctrld, ctrl4a, ctrl4b, ssn[8];
char *model;
#ifdef CONFIG_RTC_DS1685_PROC_REGS
char bits[NUM_REGS][(NUM_BITS * NUM_SPACES) + NUM_BITS + 1];
#endif
/* Read all the relevant data from the control registers. */
ds1685_rtc_switch_to_bank1(rtc);
ds1685_rtc_get_ssn(rtc, ssn);
ctrla = rtc->read(rtc, RTC_CTRL_A);
ctrlb = rtc->read(rtc, RTC_CTRL_B);
ctrlc = rtc->read(rtc, RTC_CTRL_C);
ctrld = rtc->read(rtc, RTC_CTRL_D);
ctrl4a = rtc->read(rtc, RTC_EXT_CTRL_4A);
ctrl4b = rtc->read(rtc, RTC_EXT_CTRL_4B);
ds1685_rtc_switch_to_bank0(rtc);
/* Determine the RTC model. */
switch (ssn[0]) {
case RTC_MODEL_DS1685:
model = "DS1685/DS1687\0";
break;
case RTC_MODEL_DS1689:
model = "DS1689/DS1693\0";
break;
case RTC_MODEL_DS17285:
model = "DS17285/DS17287\0";
break;
case RTC_MODEL_DS17485:
model = "DS17485/DS17487\0";
break;
case RTC_MODEL_DS17885:
model = "DS17885/DS17887\0";
break;
default:
model = "Unknown\0";
break;
}
/* Print out the information. */
seq_printf(seq,
"Model\t\t: %s\n"
"Oscillator\t: %s\n"
"12/24hr\t\t: %s\n"
"DST\t\t: %s\n"
"Data mode\t: %s\n"
"Battery\t\t: %s\n"
"Aux batt\t: %s\n"
"Update IRQ\t: %s\n"
"Periodic IRQ\t: %s\n"
"Periodic Rate\t: %s\n"
"SQW Freq\t: %s\n"
#ifdef CONFIG_RTC_DS1685_PROC_REGS
"Serial #\t: %8phC\n"
"Register Status\t:\n"
" Ctrl A\t: UIP DV2 DV1 DV0 RS3 RS2 RS1 RS0\n"
"\t\t: %s\n"
" Ctrl B\t: SET PIE AIE UIE SQWE DM 2412 DSE\n"
"\t\t: %s\n"
" Ctrl C\t: IRQF PF AF UF --- --- --- ---\n"
"\t\t: %s\n"
" Ctrl D\t: VRT --- --- --- --- --- --- ---\n"
"\t\t: %s\n"
#if !defined(CONFIG_RTC_DRV_DS1685) && !defined(CONFIG_RTC_DRV_DS1689)
" Ctrl 4A\t: VRT2 INCR BME --- PAB RF WF KF\n"
#else
" Ctrl 4A\t: VRT2 INCR --- --- PAB RF WF KF\n"
#endif
"\t\t: %s\n"
" Ctrl 4B\t: ABE E32k CS RCE PRS RIE WIE KSE\n"
"\t\t: %s\n",
#else
"Serial #\t: %8phC\n",
#endif
model,
((ctrla & RTC_CTRL_A_DV1) ? "enabled" : "disabled"),
((ctrlb & RTC_CTRL_B_2412) ? "24-hour" : "12-hour"),
((ctrlb & RTC_CTRL_B_DSE) ? "enabled" : "disabled"),
((ctrlb & RTC_CTRL_B_DM) ? "binary" : "BCD"),
((ctrld & RTC_CTRL_D_VRT) ? "ok" : "exhausted or n/a"),
((ctrl4a & RTC_CTRL_4A_VRT2) ? "ok" : "exhausted or n/a"),
((ctrlb & RTC_CTRL_B_UIE) ? "yes" : "no"),
((ctrlb & RTC_CTRL_B_PIE) ? "yes" : "no"),
(!(ctrl4b & RTC_CTRL_4B_E32K) ?
ds1685_rtc_pirq_rate[(ctrla & RTC_CTRL_A_RS_MASK)] : "none"),
(!((ctrl4b & RTC_CTRL_4B_E32K)) ?
ds1685_rtc_sqw_freq[(ctrla & RTC_CTRL_A_RS_MASK)] : "32768Hz"),
#ifdef CONFIG_RTC_DS1685_PROC_REGS
ssn,
ds1685_rtc_print_regs(ctrla, bits[0]),
ds1685_rtc_print_regs(ctrlb, bits[1]),
ds1685_rtc_print_regs(ctrlc, bits[2]),
ds1685_rtc_print_regs(ctrld, bits[3]),
ds1685_rtc_print_regs(ctrl4a, bits[4]),
ds1685_rtc_print_regs(ctrl4b, bits[5]));
#else
ssn);
#endif
return 0;
}
#else
#define ds1685_rtc_proc NULL
#endif /* CONFIG_PROC_FS */
/* ----------------------------------------------------------------------- */
/* ----------------------------------------------------------------------- */
/* RTC Class operations */
static const struct rtc_class_ops
ds1685_rtc_ops = {
.proc = ds1685_rtc_proc,
.read_time = ds1685_rtc_read_time,
.set_time = ds1685_rtc_set_time,
.read_alarm = ds1685_rtc_read_alarm,
.set_alarm = ds1685_rtc_set_alarm,
.alarm_irq_enable = ds1685_rtc_alarm_irq_enable,
};
/* ----------------------------------------------------------------------- */
/* ----------------------------------------------------------------------- */
/* SysFS interface */
#ifdef CONFIG_SYSFS
/**
* ds1685_rtc_sysfs_nvram_read - reads rtc nvram via sysfs.
* @file: pointer to file structure.
* @kobj: pointer to kobject structure.
* @bin_attr: pointer to bin_attribute structure.
* @buf: pointer to char array to hold the output.
* @pos: current file position pointer.
* @size: size of the data to read.
*/
static ssize_t
ds1685_rtc_sysfs_nvram_read(struct file *filp, struct kobject *kobj,
struct bin_attribute *bin_attr, char *buf,
loff_t pos, size_t size)
{
struct platform_device *pdev =
to_platform_device(container_of(kobj, struct device, kobj));
struct ds1685_priv *rtc = platform_get_drvdata(pdev);
ssize_t count;
unsigned long flags = 0;
spin_lock_irqsave(&rtc->lock, flags);
ds1685_rtc_switch_to_bank0(rtc);
/* Read NVRAM in time and bank0 registers. */
for (count = 0; size > 0 && pos < NVRAM_TOTAL_SZ_BANK0;
count++, size--) {
if (count < NVRAM_SZ_TIME)
*buf++ = rtc->read(rtc, (NVRAM_TIME_BASE + pos++));
else
*buf++ = rtc->read(rtc, (NVRAM_BANK0_BASE + pos++));
}
#ifndef CONFIG_RTC_DRV_DS1689
if (size > 0) {
ds1685_rtc_switch_to_bank1(rtc);
#ifndef CONFIG_RTC_DRV_DS1685
/* Enable burst-mode on DS17x85/DS17x87 */
rtc->write(rtc, RTC_EXT_CTRL_4A,
(rtc->read(rtc, RTC_EXT_CTRL_4A) |
RTC_CTRL_4A_BME));
/* We need one write to RTC_BANK1_RAM_ADDR_LSB to start
* reading with burst-mode */
rtc->write(rtc, RTC_BANK1_RAM_ADDR_LSB,
(pos - NVRAM_TOTAL_SZ_BANK0));
#endif
/* Read NVRAM in bank1 registers. */
for (count = 0; size > 0 && pos < NVRAM_TOTAL_SZ;
count++, size--) {
#ifdef CONFIG_RTC_DRV_DS1685
/* DS1685/DS1687 has to write to RTC_BANK1_RAM_ADDR
* before each read. */
rtc->write(rtc, RTC_BANK1_RAM_ADDR,
(pos - NVRAM_TOTAL_SZ_BANK0));
#endif
*buf++ = rtc->read(rtc, RTC_BANK1_RAM_DATA_PORT);
pos++;
}
#ifndef CONFIG_RTC_DRV_DS1685
/* Disable burst-mode on DS17x85/DS17x87 */
rtc->write(rtc, RTC_EXT_CTRL_4A,
(rtc->read(rtc, RTC_EXT_CTRL_4A) &
~(RTC_CTRL_4A_BME)));
#endif
ds1685_rtc_switch_to_bank0(rtc);
}
#endif /* !CONFIG_RTC_DRV_DS1689 */
spin_unlock_irqrestore(&rtc->lock, flags);
/*