-
Notifications
You must be signed in to change notification settings - Fork 570
/
common.v
76 lines (72 loc) · 2.22 KB
/
common.v
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
/*
Copyright (c) 2019 Alibaba Group Holding Limited
Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
module clk_mux2(
clk_sel,
clk_a,
clk_b,
clk_out
);
input clk_sel;
input clk_a;
input clk_b;
output clk_out;
wire clk_sel;
wire clk_a;
wire clk_b;
`ifdef FPGA
reg clk_out;
always @( clk_sel or clk_a or clk_b)
begin
case(clk_sel) // synopsys infer_mux
1'b1: clk_out = clk_b;
1'b0: clk_out = clk_a;
endcase
end
`else
wire clk_out;
Standard_Cell_CLK_MUX2 x_STD_clkmux2 (
.D0 (clk_a),
.D1 (clk_b),
.S (clk_sel),
.X (clk_out)
);
`endif
endmodule
module gated_clk_cell(
clk_in,
global_en,
module_en,
local_en,
external_en,
pad_yy_test_mode,
pad_yy_gate_clk_en_b,
clk_out
);
input clk_in;
input global_en;
input module_en;
input local_en;
input external_en;
input pad_yy_test_mode;
input pad_yy_gate_clk_en_b;
output clk_out;
wire clk_en_bf_latch;
wire SE;
reg clk_en_af_latch;
assign clk_en_bf_latch = (global_en && (module_en || local_en)) || external_en ;
assign SE = pad_yy_test_mode | pad_yy_gate_clk_en_b;
`ifdef FPGA
assign clk_out = clk_in;
`else
Standard_Cell_CLK_GATE x_gated_clk_cell(
.CK (clk_in),
.SE (SE),
.EN (clk_en_bf_latch),
.Q (clk_out)
);
`endif
endmodule