Source

[amal-khailtash]

Hi Patrick, great work for documenting VHDL. Is this available to public for consumption yet? Although I am more interested Verilog version. I was curious how involved it is to develop one for Verilog.

[Paebbels]

This is not working yet.

I'm working on a VHDL parser to extract the documentation into the ReST format. If this is working, I can try to finalize this Sphinx addon. The idea was created from my current project PoC, which is documented using Sphinx. Currently, we are using simple RegExps to extract the documentation of entities. Bus this approach does not work well with packages. That's why I'm trying to create a complete chain of Python tools / libraries from source file to the finished document.

I don't do Verilog. I'm heavily involved in the VHDL language specification at IEEE, so I won't do anything for Verilog :).

[Paebbels]

This repository (as longtime placeholder) is now actively used to create a automatic documentation extension for VHDL using Sphinx.

First proof-of-concept looks like this:

Automatic Documentation of a VHDL Entity

Please see #5 for more details.