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Commits on Jan 12, 2023

• link test action to this repo

  pbrazzle

  authoredJan 12, 2023
  7c3776c

• logging interrupt

  pbrazzle

  committedJan 12, 2023
  cc426fd

• Merge branch 'master' of https://github.com/Pitt-JonesLab/litedram-tmr

  pbrazzle

  committedJan 12, 2023
  7f83a1b

• Added function to generate log signals for tracking rising edge

  pbrazzle

  committedJan 12, 2023
  ec416c3

Commits on Jan 11, 2023

• Merge pull request #7 from enjoy-digital/master

  pbrazzle

  authoredJan 11, 2023
  ecc377b

• Merge pull request enjoy-digital#321 from antmicro/msieron/sdram-hw-test

  enjoy-digital

  authoredJan 11, 2023
  b749e10

• test/common: fix expected data for test_bist.py

  michalsieron

  committedJan 11, 2023
  dad2c97

• Moved logging.py

  

  percs

  authored and

  percs

  committedJan 11, 2023
  1211ec9

• Moved logging.py

  

  percs

  authored and

  percs

  committedJan 11, 2023
  f49352a

• Delete logging.py

  pbrazzle

  authoredJan 11, 2023
  3bd0236

• added logging system

  

  percs

  authored and

  percs

  committedJan 11, 2023
  d0aa463

• Added logging system

  

  percs

  authored and

  percs

  committedJan 11, 2023
  55ffd7a

• frontend/bist: make LFSR output comb

  michalsieron

  committedJan 11, 2023
  73c3ec6

• frontend/bist: replicate LFSR output to fill DRAM port

  michalsieron

  committedJan 11, 2023
  f466c5f

• gen: increase ROM size

  michalsieron

  committedJan 11, 2023
  89581c1

Commits on Jan 10, 2023

• Merge pull request #1 from enjoy-digital/master

  pbrazzle

  authoredJan 10, 2023
  a2862db

• test/test_init: Update.

  enjoy-digital

  committedJan 10, 2023
  69b401d

• Merge pull request enjoy-digital#320 from antmicro/msieron/sdram-spd

  enjoy-digital

  authoredJan 10, 2023
  d17b021

Commits on Jan 9, 2023

• init: define SDRAM_PHY_SUPPORTED_MEMORY

  michalsieron

  committedJan 9, 2023
  8fa3253

• init: define SDRAM_PHY_[DDR3|DDR4|...]

  michalsieron

  committedJan 9, 2023
  4c9f184

Commits on Jan 7, 2023

• New README

  pbrazzle

  authoredJan 7, 2023
  1eae82d

Commits on Jan 5, 2023

• Merge pull request enjoy-digital#319 from antmicro/msieron/fix-bist-errors

  enjoy-digital

  authoredJan 5, 2023
  8339f54

Commits on Jan 4, 2023

• frontend/bist: properly signal finished writes

  michalsieron

  committedJan 4, 2023
  f45ca41

Commits on Dec 9, 2022

• ci: Switch to ubuntu 22.04 and increase similarities with LiteX's CI.

  enjoy-digital

  committedDec 9, 2022
  3b2bcf9

Commits on Dec 8, 2022

• ci: Install RISC-V GCC with litex_setup.py.

  enjoy-digital

  committedDec 8, 2022
  6b00d1a

• bench: Update with LiteX/LiteX-Boards changes.

  enjoy-digital

  committedDec 8, 2022
  379db85

Commits on Nov 18, 2022

• Merge pull request enjoy-digital#314 from antmicro/msieron/fix-ddr4-sim

  enjoy-digital

  authoredNov 18, 2022
  1f1ab2d

Commits on Nov 14, 2022

• Fix DFITimingsChecker for DDR4 simulation

  michalsieron

  committedNov 14, 2022
  f25604c

Commits on Oct 25, 2022

• test/test_lpddr5: Add tINIT2 as allowed warning.

  enjoy-digital

  committedOct 25, 2022
  c770dd6

Commits on Oct 14, 2022

• ci: Bump to ubuntu 20.04.

  enjoy-digital

  committedOct 14, 2022
  d1529d7

Commits on Sep 15, 2022

• axi: Update frontend/test with LiteX changes.

  enjoy-digital

  committedSep 15, 2022
  ae0763e

Commits on Sep 8, 2022

• phy/gw2ddrphy: Minor cosmetic cleanups.

  enjoy-digital

  committedSep 8, 2022
  559dd24

• phy/gw2ddrphy: Add explicit TXCLK_POL and set it to 1 for DQS.

  enjoy-digital

  committedSep 8, 2022
  cff8500

• gw2ddrphy: Add TCLK_SOURCE on DQS's OSER4_MEM.

  enjoy-digital

  committedSep 8, 2022
  5b72d1a

Commits on Sep 7, 2022

• phy/gw2ddrphy: Make oen signal names consistent.

  enjoy-digital

  committedSep 7, 2022
  ab9aec9

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