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DSP_DSP2833x_Xintf.c
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DSP_DSP2833x_Xintf.c
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// TI File $Revision: /main/5 $
// Checkin $Date: August 16, 2007 11:06:26 $
//###########################################################################
//
// FILE: DSP2833x_Xintf.c
//
// TITLE: DSP2833x Device External Interface Init & Support Functions.
//
// DESCRIPTION:
//
// Example initialization function for the external interface (XINTF).
// This example configures the XINTF to its default state. For an
// example of how this function being used refer to the
// examples/run_from_xintf project.
//
//###########################################################################
// $TI Release: DSP2833x/DSP2823x C/C++ Header Files V1.31 $
// $Release Date: August 4, 2009 $
//###########################################################################
#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File
#include "DSP2833x_Examples.h" // DSP2833x Examples Include File
//---------------------------------------------------------------------------
// InitXINTF:
//---------------------------------------------------------------------------
// This function initializes the External Interface the default reset state.
//
// Do not modify the timings of the XINTF while running from the XINTF. Doing
// so can yield unpredictable results
void InitXintf(void)
{
// This shows how to write to the XINTF registers. The
// values used here are the default state after reset.
// Different hardware will require a different configuration.
// For an example of an XINTF configuration used with the
// F28335 eZdsp, refer to the examples/run_from_xintf project.
// Any changes to XINTF timing should only be made by code
// running outside of the XINTF.
// All Zones---------------------------------
// Timing for all zones based on XTIMCLK = 1/2 SYSCLKOUT
EALLOW;
XintfRegs.XINTCNF2.bit.XTIMCLK = 1;
// No write buffering
XintfRegs.XINTCNF2.bit.WRBUFF = 0;
// XCLKOUT is enabled
XintfRegs.XINTCNF2.bit.CLKOFF = 0;
// XCLKOUT = XTIMCLK/2
XintfRegs.XINTCNF2.bit.CLKMODE = 1;
XintfRegs.XINTCNF2.bit.HOLD = 1;
// Zone 0------------------------------------
// When using ready, ACTIVE must be 1 or greater
// Lead must always be 1 or greater
// Zone write timing
XintfRegs.XTIMING0.bit.XWRLEAD = 3;
XintfRegs.XTIMING0.bit.XWRACTIVE = 7;
XintfRegs.XTIMING0.bit.XWRTRAIL = 3;
// Zone read timing
XintfRegs.XTIMING0.bit.XRDLEAD = 3;
XintfRegs.XTIMING0.bit.XRDACTIVE = 7;
XintfRegs.XTIMING0.bit.XRDTRAIL = 3;
// double all Zone read/write lead/active/trail timing
XintfRegs.XTIMING0.bit.X2TIMING = 1;
// Zone will sample XREADY signal
XintfRegs.XTIMING0.bit.USEREADY = 0;
XintfRegs.XTIMING0.bit.READYMODE = 1; // sample asynchronous
// Size must be either:
// 0,1 = x32 or
// 1,1 = x16 other values are reserved
XintfRegs.XTIMING0.bit.XSIZE = 3;
// Zone 6------------------------------------
// When using ready, ACTIVE must be 1 or greater
// Lead must always be 1 or greater
// Zone write timing
XintfRegs.XTIMING6.bit.XWRLEAD = 3;
XintfRegs.XTIMING6.bit.XWRACTIVE = 7;
XintfRegs.XTIMING6.bit.XWRTRAIL = 3;
// Zone read timing
XintfRegs.XTIMING6.bit.XRDLEAD = 3;
XintfRegs.XTIMING6.bit.XRDACTIVE = 7;
XintfRegs.XTIMING6.bit.XRDTRAIL = 3;
// double all Zone read/write lead/active/trail timing
XintfRegs.XTIMING6.bit.X2TIMING = 1;
// Zone will sample XREADY signal
XintfRegs.XTIMING6.bit.USEREADY = 0;
XintfRegs.XTIMING6.bit.READYMODE = 1; // sample asynchronous
// Size must be either:
// 0,1 = x32 or
// 1,1 = x16 other values are reserved
XintfRegs.XTIMING6.bit.XSIZE = 3;
// Zone 7------------------------------------
// When using ready, ACTIVE must be 1 or greater
// Lead must always be 1 or greater
// Zone write timing
XintfRegs.XTIMING7.bit.XWRLEAD = 3;
XintfRegs.XTIMING7.bit.XWRACTIVE = 7;
XintfRegs.XTIMING7.bit.XWRTRAIL = 3;
// Zone read timing
XintfRegs.XTIMING7.bit.XRDLEAD = 3;
XintfRegs.XTIMING7.bit.XRDACTIVE = 7;
XintfRegs.XTIMING7.bit.XRDTRAIL = 3;
// not double all Zone read/write lead/active/trail timing
XintfRegs.XTIMING7.bit.X2TIMING = 0;
// Zone will sample XREADY signal
XintfRegs.XTIMING7.bit.USEREADY = 0;
XintfRegs.XTIMING7.bit.READYMODE = 1; // sample asynchronous
// Size must be either:
// 0,1 = x32 or
// 1,1 = x16 other values are reserved
XintfRegs.XTIMING7.bit.XSIZE = 3;
// Bank switching
// Assume Zone 7 is slow, so add additional BCYC cycles
// when ever switching from Zone 7 to another Zone.
// This will help avoid bus contention.
XintfRegs.XBANK.bit.BANK = 7;
XintfRegs.XBANK.bit.BCYC = 7;
EDIS;
//Force a pipeline flush to ensure that the write to
//the last register configured occurs before returning.
asm(" RPT #7 || NOP");
}
//===========================================================================
// No more.
//===========================================================================